Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2011-06-21
2011-06-21
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C710S100000, C710S305000, C710S306000, C710S315000, C713S400000, C713S401000
Reexamination Certificate
active
07966468
ABSTRACT:
A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.
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Srinivasan Anand
Surgutchik Roman
Titus Joshua
Choe Yong
Cooley LLP
Dillon Samuel
Nvidia Corporation
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