Apparatus, system, and method for bus link width optimization

Details Apparatus, system, and method for bus link width optimization Apparatus, system, and method for bus link width optimization

2006-11-14

2006-11-14

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S029000

Reexamination Certificate

active

07136953

ABSTRACT:
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

REFERENCES:
patent: 5951664 (1999-09-01), Lambrecht et al.
patent: 2004/0088469 (2004-05-01), Levy
patent: 2004/0210687 (2004-10-01), Mann
patent: 1146429 (2001-10-01), None
Gerald Holzhammer, Intel, Developer Update Magazine, “Creating a Third Generation I/O Bus,” Sep. 2001, pp. 1-5, Copyright © Intel Corporation 2001.
Seh Kwa and Debra T. Cohen—Intel Corporation, “PCI Express, Architecture Power Management,” Nov. 8, 2002, pp. 1-14, Copyright © Intel Corporation 2002.
PCI EXPRESS, “Base Specification,” Revision 1.0a, Apr. 15, 2003, pp. 1-426, Copyright © 2002, 2003, PCI-SIG.
Ajy V. Bhatt (Technology and Research Labs, Intel Corporation), “Creating a Third Generation I/O Interconnect,” pp. 1-8. Copyright © 2002.

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