Apparatus, system, and method for avoiding data writes that...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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C710S052000, C718S104000

Reexamination Certificate

active

07054987

ABSTRACT:
A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.

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“A novel reordering write buffer to improve write performance of log-structured file systemn” by Jun Wang and Yiming Hu□□(abstract only) Publication Date: Dec. 2003.
Shanley, “Pentium® Pro and Pentium® II System Architecture,” Second Edition,Addison-Wesley, ©1998 by MindShare, Inc., 6thprinting Jan. 2001, Chapter 8 to 13 (199-348).

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