Computer graphics processing and selective visual display system – Computer graphics display memory system – Shared memory
Reexamination Certificate
2008-05-06
2008-05-06
Tung, Kee M. (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Shared memory
C345S544000, C345S535000, C345S531000
Reexamination Certificate
active
07369133
ABSTRACT:
A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions. In one embodiment, an additional arbiter circuit selects memory requests from one of a subset of the memory clients and forwards the requests to a routing circuit, thereby providing a way for the subset of memory clients to share the client queues and routing circuit. Alternatively, a memory client can make requests directed to a particular partition in which case no routing circuit is required. For a read request that requires more than one partition to service, the memory system must collect the read data from read queues for the various partitions and deliver the collected data back to the proper client. Read queues can provide data in non-fifo order to satisfy an memory client that can receive data out-of-order.
REFERENCES:
patent: 5109520 (1992-04-01), Knierim
patent: 5408606 (1995-04-01), Eckart
patent: 5452299 (1995-09-01), Thessin et al.
patent: 5485586 (1996-01-01), Brash et al.
patent: 5500939 (1996-03-01), Kurihara
patent: 5572655 (1996-11-01), Tuljapurkar et al.
patent: 5623688 (1997-04-01), Ikeda et al.
patent: 5625778 (1997-04-01), Childers et al.
patent: 5664162 (1997-09-01), Dye
patent: 5898895 (1999-04-01), William
patent: 5905877 (1999-05-01), Guthrie et al.
patent: 5923826 (1999-07-01), Grzenda et al.
patent: 6104417 (2000-08-01), Nielsen et al.
patent: 6115323 (2000-09-01), Hashimoto
patent: 6157963 (2000-12-01), Courtright et al.
patent: 6157989 (2000-12-01), Collins et al.
patent: 6202101 (2001-03-01), Chin et al.
patent: 6205524 (2001-03-01), Ng
patent: 6219725 (2001-04-01), Diehl et al.
patent: 6469703 (2002-10-01), Aleksic et al.
patent: 6545684 (2003-04-01), Dragony et al.
patent: 6570571 (2003-05-01), Morozumi
patent: 6853382 (2005-02-01), Van Dyke et al.
Molnar Steven E.
Montrym John S.
Van Dyke James M.
Cooley Godward Kronish LLP
Nguyen Hau H
Nvidia Corporation
Tung Kee M.
LandOfFree
Apparatus, system, and method for a partitioned memory for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus, system, and method for a partitioned memory for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus, system, and method for a partitioned memory for a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2755519