Apparatus, system, and method for a fast data return memory...

Details Apparatus, system, and method for a fast data return memory... Apparatus, system, and method for a fast data return memory...

2011-06-21

2011-06-21

Zaman, Faisal M (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S006000, C710S058000, C711S167000

Reexamination Certificate

active

07966439

ABSTRACT:
A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.

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