Apparatus of reducing power consumption of single-ended SRAM

Details Apparatus of reducing power consumption of single-ended SRAM Apparatus of reducing power consumption of single-ended SRAM

2000-11-21

2001-10-16

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S227000

Reexamination Certificate

active

06304482

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to an apparatus of reducing power consumption of a single-ended Static Random Access Memory.
B. Description of the Related Art
FIG. 1
shows a circuit diagram of memory cell in a conventional single-ended Static Random Access Memory (hereinafter referred as SRAM). When a word line is asserted, a single bit data is either written into or read from an inverter
112
of a memory cell
110
connected with the word line through a bit line. In comparison with a two-ended SRAM using six transistors, a single-ended SRAM occupies less chip area with relatively low manufacturing cost because a single-ended SRAM consists of five transistors that are included in two inverters
111
,
112
and one pass transistor
113
.
FIG. 2
shows a schematic structural diagram of a memory cell array using single-ended SRAM for data storage. The SRAM cell array
100
consists of memory cells
110
arranged in a form of array, and “a word line and a bit line” for controlling both the data writing and the data reading of the memory cells
110
. Same row of memory cells
110
are connected to the same word line while same column of memory cells
110
are connected to the same bit line in the SRAM cell array
100
. Therefore, when a word line is asserted, the data is written into or read from the same row of memory cells
110
through different bit lines. Since every bit line connects many memory cells
110
, a relatively higher capacitance is constituted therefor. Thus, it takes relatively long time for a bit line to shift its status from 0 bit to 1 bit or vice versa.
As shown in
FIG. 3
, in order to increase the speed of shifting status of a bit line, a load and pre-charging cell is added into the bit line. Before data reading or data writing, the pre-charging cell
140
will charge the bit line to be a status of 1 bit. Then, if the reading data or writing data is 1 bit, the status of the bit line will remain as 1 bit, and, on the other hand, if the reading data or writing data is 0 bit, the status of the bit line will be shifted to 0 bit. Since the bit lines have relatively higher capacitance, it will consume a considerable amount of power for a bit line to shift the status from 1 bit to 0 bit, or vice versa. Thus, when a single-ended SRAM with large capacity is employed, the power consumption has become a serious problem. Therefore, if it is possible to reduce the ratio of 0 bits of the data to be stored in the single-ended SRAM, it can reduce the power consumption thereby.
SUMMARY OF THE INVENTION
Aiming at the problem mentioned above, one of objects of the present invention is to provide an apparatus of reducing power consumption of single-ended SRAM.
Another object of the present invention is to provide an apparatus of reducing power consumption of single-ended SRAM that a written data is converted into a storage data with a majority of 1 bits. Then, the storage data is stored in the single-ended SRAM in order to reduce the power consumption of the single-ended SRAM.
The apparatus of reducing power consumption of single-ended SRAM according to the present invention consists of at least an extra column of SRAM, a majority detector for detecting a bit status of the written data and for writing the value of the bit status into the extra column of SRAM. The apparatus further includes a data scrambler that converts the written data into a storage data with a minority of 0 bits based on the bit status of the written data and writes the storage data into the single-ended SRAM. And, the apparatus further includes a data de-scrambler that converts the storage data read from the single-ended SRAM into its original format based on the correspondent bit status stored in the extra column of SRAM and outputs the data in its original format. Because a majority of 1 bits is kept in the storage data stored in the single-ended SRAM, thereby it can reduce the power consumption of the single-ended SRAM.


REFERENCES:
patent: 5805496 (1998-09-01), Batson et al.
patent: 5831896 (1998-11-01), Lattimore et al.
patent: 5986923 (1999-11-01), Zhang et al.

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