Apparatus, methods, and system of NAND defect management

Details Apparatus, methods, and system of NAND defect management Apparatus, methods, and system of NAND defect management

2011-08-02

2011-08-02

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07992060

ABSTRACT:
Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

REFERENCES:
patent: 5239681 (1993-08-01), Parnall et al.
patent: 6192072 (2001-02-01), Azadet et al.
patent: 7315917 (2008-01-01), Bennett et al.
patent: 7669092 (2010-02-01), Murray
patent: 2005/0144516 (2005-06-01), Gonzalez et al.
patent: 2006/0161724 (2006-07-01), Bennett et al.
patent: 2006/0161728 (2006-07-01), Bennett et al.
patent: 2008/0091872 (2008-04-01), Bennett et al.
patent: 2008/0209107 (2008-08-01), Murray
patent: 1564755 (2005-08-01), None
patent: WO-2008106095 (2008-09-01), None
“European Application Serial No. 08726059.2, Office Action mailed May 6, 2010”, 3 pgs.

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