Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1995-07-24
2003-06-10
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S760020
Reexamination Certificate
active
06577148
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to test apparatus and methods, and more particularly, semiconductor wafer testing and stimulus.
BACKGROUND OF THE INVENTION
Wafer Level Burn-in consists basically of a sacrificial layer of metal added to the wafer after normal processing has ended. This sacrificial layer of metal is added to provide the required electrical stimulus to the devices on the wafer to exercise functional circuitry providing a level of transistor operation along with elevated temperatures for a period of time determined to stress and detect “early fail” or weak transistors up front before shipping product integrated circuits (ICs). The elevated temperature and electical stimulus accelerates the failure mechanisms associated with certain weak devices. If the device is functional after burn-in, then it contains none of the defects associated with early feild reliablity failures. It has passed the point in time that typical early reliability failures will fail in the field (i.e., in customer's systems).
Problems concerning the prior art of sacrificial metal includes additional product wafer processing, removal of sacraficial metal which may cause unforeseen reliability problems, and the wafer after deprocessing is essentially a different product that what was burned-in.
The sacraficial metal layer will require a wafer layer planarization process prior to sacrificial metal deposition to eliminate issues with depth of focus for photoresist exposure and topography which can cause metal-to-metal defects. Typically, final metal deposition with oxide
itride passivation creates severe topography that may cause metal shorts on the sacrificial metal layer as well as photo resist patterning problems. To improve the sacrificial metal yield, a planarization process is needed to reduce the topographical features. This planarization step is non-typical wafer processing. Vias need to be etched to reach the final metal layer for the sacrificial metal connection. This final metal layer of the product usually contains metal bonding pads. Sacrificial metal is then deposited and patterned to form the bussing network to the individual die. This sacrificial metal layer is then connected to electric stimuli during a high temperature burn-in. After the wafer is burned-in, the sacrificial metal layer has to be etched away to expose the original bonding pad and the wafer is then electrically tested at wafer probe test. All sacrificial metal layer deposition and photoresist application and exposure processes must be done in the IC fabrication facility to eliminate equipment contamination.
Reliability problems may exist due to sacrificial metal removal effects on the last metal bond pads due to metal thinning unless a carefully controlled, timed metal etch process is used. Since the sacrificial metal layer has the same material properties of the final metal bond pad, there is no automatic etch stop. This could affect the wirebond reliability as compared to a device that did not have the sacrificial metal method of wafer level burn-in. Additional reliability problems could exist by the absence of a deposited polyimide stress layer as required for certain types of plastic packages. This process could be added after sacrificial metal removal but in most cases, wafers are not allowed back into the IC wafer fabrication facility once removed due to equipment contamination concerns. The addition of a polyimide layer would have to be done in a relatively dirty environment as compared to the wafer IC fabrication facility conditions and cause reliability concerns due to contamination (sodium, potassium, etc. . . ).
Assuming all of the extra wafer processing and reliability concerns could be overlooked, there is still the fundamental problem that extra processing has occurred to the wafer after burn-in. Essentially, the burned-in wafer has different processing than the finished product after sacrificial metal removal.
Once it has been determined that a sacrificial metal layer burn-in will be used on a product, a test strategy must be designed. This can be accomplished by a couple of methods.
One method is to use complex test circuitry in the burn-in test system. This is costly and maintenance intensive. During the manufacturing/production mode of product lifetime, reliability studies are seldom performed or monitored except at small sample levels. If the test circuitry of the burn-in oven has problems, an IC wafer fabrication lot may not have been burned-in properly which is a reliability issue. In a sample methodology, a relatively small number of devices are removed from each product lot to have a reliability study done. Typically, this reliability study may take several weeks of collecting samples from multiple product lots before a sufficient quantity has been collected to release production equipment to the reliability study. Once a reliability problem has been found with a product lot, it may be several weeks after the product has been shipped to the customer and product recall must occur once the monitored study has been completed. This burn-in methodology has severe product reliability and customer satisfaction issue.
Another method to reduce the burn-in equipment reliability issue is to add additional built-in self test circuitry (BIST). While this method could eliminate some embarrassing problems in product development, it will take up valuable silicon surface area and add cost to each device. Additionally, the extra design resources and time to develop the BIST circuitry may have implications for new product development time to market.
Typical device burn-in has historically been done in a packaged part form. Usually, the burn-in occurs overseas (Malaysia, Thailand, etc. . . ). This is a time consuming process where each individual package unit must be mounted on a burn-in test card and loaded into a burn-in oven. The device must be burned-in and then tested afterwards to see if it is still functional. If the device is non-functional, the part will be discarded and the additional test time and package materials/cost are lost. This could be quite costly for new IC fabrication facility processes depending on the burn-in failure rate due to the relative reliability maturity of the IC fabrication facility process.
Additional problems with the historic approach concern reliability studies. During a monitored burn-in study that typically occurs during new product development, devices have to be removed from the oven at timed intervals (every 6 or 12 hours depending on the accuracy of the study) and tested for functionality. This is a very tedious task and very time consuming thereby allowing for numerous opportunities for error (lost parts, bent package leads, etc . . . ). The time consumed and accuracy during the study could adversely affect time to market and reliability levels for new products. Therefore, a new and more effective/cost efficient way to test ICs is needed.
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DeHaven Robert Keith
Wenzel James F.
Clingan, Jr. James L.
Karlsen Ernest
Witek Keith E.
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