Apparatus, method, and system of NAND defect management

Details Apparatus, method, and system of NAND defect management Apparatus, method, and system of NAND defect management

2007-02-26

2010-02-23

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000, C714S819000, C365S185330

Reexamination Certificate

active

07669092

ABSTRACT:
Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group.

REFERENCES:
patent: 7315917 (2008-01-01), Bennett et al.
patent: 2005/0144516 (2005-06-01), Gonzalez et al.
patent: 2006/0161724 (2006-07-01), Bennett et al.
patent: 2006/0161728 (2006-07-01), Bennett et al.
patent: 2008/0091872 (2008-04-01), Bennett et al.
patent: 1564755 (2005-08-01), None
patent: WO-2008106095 (2008-09-01), None

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