Apparatus, method, and system for reducing latency of memory...

Details Apparatus, method, and system for reducing latency of memory... Apparatus, method, and system for reducing latency of memory...

2005-05-10

2005-05-10

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S168000, C711S169000, C711S154000, C712S207000

Reexamination Certificate

active

06892281

ABSTRACT:
According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.

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