Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-10-23
2007-10-23
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S503000
Reexamination Certificate
active
10444749
ABSTRACT:
An apparatus, a method and a storage medium for carrying out a deskew among multiple lanes for use in a division transmission of large-capacity data. The method comprises the steps of detecting alignment characters from data streams on a lane-by-lane basis, determining whether a skew among the lanes is generated by comparing reception points of the alignment characters for respective lanes, if the skew among the lanes is generated, storing the alignment characters in a first storage column of a shift register on the lane-by-lane basis and storing data being subsequent to the alignment characters in a second storage column, at a time of a last alignment character detection, setting a last storage section on the lane-by-lane basis and indicating an alignment completion, shifting the data to output the data stored in the first storage column when the data is inputted into the last storage section, and intactly outputting the data streams before the deskew is completely accomplished in the storage device and outputting the aligned data streams after the deskew is completely accomplished.
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Jung Hae Won
Kang Sung Soo
Kim Dae Up
Lee Hyeong Ho
Blakely & Sokoloff, Taylor & Zafman
Brown Michael J.
Electronics and Telecommunications Research Institute
Perveen Rehana
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