Apparatus, method, and program for verifying logic circuit...

Details Apparatus, method, and program for verifying logic circuit... Apparatus, method, and program for verifying logic circuit...

2008-01-22

2010-11-23

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S019000

Reexamination Certificate

active

07840924

ABSTRACT:
A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay generator inserter produces a delay-insertable version of the circuit by embedding a delay generator into each found CDC path. When activated, those delay generators give a signal delay to the corresponding CDC paths. A simulator simulates the behavior of the delay-insertable circuit by using a specified simulation pattern while deactivating the embedded delay generators. A delay pattern generator creates a delay pattern from simulation results, which activates or deactivates delay generators individually so as to produce signal delays that could affect output signals of the circuit. A verifier verifies the circuit by applying the delay pattern to each delay generator in the circuit.

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“Clock Domain Crossings (CDC)”, http://www.metorg.co.jp.techpaper/cdc/index.html.
“O-In Clock-Domain Crossing”, Advanced Verification and Debugging DataSheet, http://www.mentorg.co.jp.

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