Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-01-17
2004-08-17
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06779160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus, a method and a pattern for evaluating characteristics of semiconductor devices. More particularly, the invention relates to an apparatus, a method and a pattern for evaluating characteristics of MOSFETs (metal oxide semiconductor field effect transistors).
2. Description of the Background Art
In order to operate large-scale integrated circuits (LSIs) at high speeds, it is necessary to boost the ability of MOSFETs contained in the LSIs to drive currents. The requirement has been met conventionally by measures such as reducing the gate lengths L of the MOSFETs or devising a suitable structure of source-drain (S/D) regions therein.
FIGS. 13A and 13B
are a plan view and a cross-sectional view of a conventional NchMOSFET having a lightly doped drain (LDD) structure. The illustrated MOSFET comprises a channel region
12
covered with a gate electrode
10
and an S/D diffusion layer
14
formed on both sides of the channel region
12
. The S/D diffusion layer
14
has an n+ layer
16
and an n− layer
18
. The n+ layer
16
contains N-type impurities at a relatively high density, and the n− layer
18
has N-type impurities at a relatively low density. The MOSFET also includes contacts
20
which are formed a predetermined distance apart from the gate electrode
10
and which conduct electrically to the S/D diffusion layer
14
.
In
FIGS. 13A and 13B
, reference character W stands for a channel width; L for a gate length as well as a total length of the gate electrode
10
; Lgc for a distance between one side of the gate electrode
10
on the one hand and the contacts
20
on the other hand; and Leff for an effective channel length of the MOSFET. In addition, reference character Rdsw denotes a resistance value per unit width of the S/D diffusion layer
14
in a portion where the layer
14
overlaps with the gate electrode
10
(the overlapping portion resistance value), and reference character Rsh represents a sheet resistance value of the S/D diffusion layer
14
where the layer
14
does not overlap with the gate electrode
10
. The overlapping portion resistance value Rdsw is determined primarily by the resistance value of the n− layer
18
. The sheet resistance value Rsh is determined by the sheet resistance value of the n+ layer
16
.
The current driving capability of an MOSFET is determined primarily by its effective channel length Leff, its overlapping portion resistance value Rdsw and its sheet resistance value Rsh. It follows that in order to stabilize the quality of MOSFETs by accurately managing their current driving capabilities, it is necessary to measure such characteristic values with precision.
FIGS. 14A and 14B
are a plan view and a cross-sectional view of a typical measurement pattern used conventionally to measure sheet resistance. The illustrated measurement pattern allows sheet resistance values to be measured in a Y direction in
FIG. 14A
but does not permit resistance measurement in an X direction in FIG.
14
B. Of the critical characteristic values determining the current driving capability of the MOSFET, the overlapping portion resistance value Rdsw has thus proved especially difficult to measure with ease and precision.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to overcome the above and other deficiencies of the related art and to provide a characteristic evaluation apparatus of the semiconductor device suitable for measuring easily and accurately such characteristic values as the above-mentioned overlapping portion resistance value Rdsw and sheet resistance value Rsh.
It is a second object of the present invention to provide a characteristic evaluation method suitable for measuring easily and accurately such characteristic values as the overlapping portion resistance value Rdsw and sheet resistance value Rsh.
It is a third object of the present invention to provide a characteristic evaluation pattern suitable for measuring easily and accurately such characteristic values as the overlapping portion resistance value Rdsw and sheet resistance value Rsh.
The above objects of the present invention are achieved by.
The above objects of the present invention are achieved by.
The above objects of the present invention are achieved by.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 4939681 (1990-07-01), Yokomizo et al.
patent: 5404309 (1995-04-01), Yamamoto et al.
patent: 6110219 (2000-08-01), Jiang
patent: 54-26667 (1979-02-01), None
patent: 11-214463 (1999-08-01), None
patent: 02001313323 (2001-11-01), None
“A New Variational Method to Determine Effective Channel Length and Series Resistance of MOSFETs”, K. Yamaguchi et al., Proc. IEEE 1998 Int. Conference on Microelectronic Text Structures, vol. 11, Mar. 1998, pp. 123-126.
Amishiro Hiroyuki
Yamaguchi Kenji
Bowers Brandon
Garbowski Leigh M.
McDermott Will & Emery LLP
Renesas Technology Corp.
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