Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-06-23
2001-05-15
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S020000, C710S108000, C710S120000, C712S032000, C712S035000, C712S043000, C709S217000, C709S218000, C709S219000, C709S249000, C709S250000, C370S362000, C370S463000, C370S902000, C379S093030, C379S093240, C379S093240, C379S093240
Reexamination Certificate
active
06233643
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a time division multiplexing communications adapter, and more particularly to such an adapter, including a number of digital signal processors, which may be used as a member of an interconnected group of such adapters.
2. Background Information
A conventional DSP (Digital Signal Processor) based communications system having a capability of handling large numbers of channels on one or more network lines includes a line card to which one or more external lines may be attached and one or more DSP cards which can be used for adding processor resource to the line card. However, since network lines can carry varying numbers of information channels, and since information networks can be expected to grow and otherwise change in a number of ways, a problem with this approach is its lack of flexibility. A user of this type of system cannot vary the number of lines which can be attached to his system to match his processing capability without increasing his number of line cards.
What is needed is a communications card which has both line adapter functions and DSP resources, with such a card being readily connectable with a second communications card to increase the DSP resources available for a network line attached to the second communications card.
What is needed is a communications card which communicates with an external processor, such as the processor of a host controller card, or a system unit processor, by means of interrupts. The communications adapter may have a number of DSPs. Due to the real-time nature of processor operation, the overhead of handling interrupts may become a serious burden. When a single host, or controller, processor is connected to many DSPs in the communications card, a major overhead problem for the host processor is due to a need for context switching and due to a need to save and restore all registers for each interrupt. Problems with this burden are particularly significant when the host processor is a RISC configuration having a large number of registers to be saved.
What is needed is a method for bundling a number of interrupts to the host processor from a single DSP, so that they can be handled together.
3. Description of the Prior Art
U.S. Pat. No. 4,991,169 describes the use of a dual digital signal processor (DSP) to provide real-time links between multiple time division channels of a digital carrier system (e.g. T−1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the host processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users, remotely linked to the carrier system via the switched public network. At the host interface, signals are transmitted and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters. The DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, and selective muting of voice to host storage for voice mail applications.
U.S. Pat. No. 5,553,293 describes an interprocessor interrupt unit (IIU) for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off-loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor packs a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU receives a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed. The IIU may be programmed to notify the remote processor of completion either by an interrupt or by setting a status flag in the DRAM.
U.S. Pat. No. 5,572,695 describes a digital signal processing system including first and second logical memory mapping units coupled to first and second digital processors, respectively, and to a data storage unit. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.
SUMMARY OF THE INVENTION
It is a first objective of the present invention to provide an adapter in which DSPs resident on multiple cards communicate through PCI and TDM busses, so that the work of processing data transmitted at a primary rate can be easily distributed among two or more DSPs.
It is another objective of the present invention to provide a TDM (time division multiplexing) interface for data from an on-card primary interface or an off-card source, such as similar adapters or a line card.
It is another objective of the present invention to allow channelized TDM traffic to be diverted to available DSPs in response to MIP (process speed) and memory requirements.
It is another objective of the present invention to provide a TDM interface having access to multiple primary interfaces.
It is another objective of the present invention to provide for communications between a host controller card and DSPs as well as among DSPs.
It is another objective of the invention to provide a system in which interrupt process can optionally be bundled according to system needs.
It is another objective of the invention to provide for the use of a PCI (Peripheral Component Interconnect) bus by both the host controller and the system unit processor, allowing interrupts to pass between DSPs and the host controller as well as the system unit processor.
In accordance with one aspect of the invention, there is provided first and second communications adapters and a first bus extending between these communications adapters. Each of the communications adapters includes network interfacing circuits for connection of a telephone network line, time division multiplexing circuits combining a number of signals for transmission along the telephone line, time division demultiplexing circuits separating a number of signals received from the telephone network line, and a number of digital signal processors connected to the time division multiplexing circuits and to the time division demultiplexing circuits. The first bus connects the number of digital signal processors of the first communications adapter with the time division multiplexing and demultiplexing means of the second communications adapter, and connects the number of digital signal processors on the second communications adapter with the time division multiplexing and demultiplexing circuits of the first communications adapter.
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Andrews Lawrence P.
Beckman Richard Clyde
Eng Robert Chih-Tsin
Linger Judith Marie
Petty, Jr. Joseph C.
Davidge Ronald V.
International Business Machines - Corporation
Jean Frantz Blanchard
Sheikh Ayaz R.
Tomlin Richard A.
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