Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-08-17
2008-10-07
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C365S185010
Reexamination Certificate
active
07432546
ABSTRACT:
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.
REFERENCES:
patent: 4769340 (1988-09-01), Chang et al.
patent: 4980307 (1990-12-01), Ito et al.
patent: 5120670 (1992-06-01), Bergmont
patent: 5132756 (1992-07-01), Matsuda
patent: 5292673 (1994-03-01), Shinnki et al.
patent: 5360760 (1994-11-01), Thakur et al.
patent: 5376593 (1994-12-01), Sandhu et al.
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5393683 (1995-02-01), Mathews et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5405805 (1995-04-01), Homma
patent: 5407870 (1995-04-01), Okada et al.
patent: 5434813 (1995-07-01), Tamura et al.
patent: 5756392 (1998-05-01), Lu et al.
patent: 5837585 (1998-11-01), Wu et al.
patent: 6046085 (2000-04-01), Chan
patent: 6063666 (2000-05-01), Chang et al.
patent: 6071784 (2000-06-01), Mehta et al.
patent: 6096604 (2000-08-01), Cha et al.
patent: 6153470 (2000-11-01), He et al.
patent: 6255205 (2001-07-01), Sung
patent: 6348380 (2002-02-01), Weimer et al.
Muramatsu et al., “The Solution of over-erase problem controlling Poly-Si grain size-Modified scaling principles for Flash memory”, IEEE Technical digest IEDM 1994, pp. 847-850.
Muramatsu et al., (“The Solution of over-erase problem controlling Poly-Si grain size-Modified scaling principles for Flash memory”, IEEE Technical digest IEDM 1994, pp. 847-850).
McKee Jeff A.
Moore John T.
Powell Don C.
Weimer Ronald A.
Jackson Jerome
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Valentine Jami M
LandOfFree
Apparatus having a memory device with floating gate layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus having a memory device with floating gate layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus having a memory device with floating gate layer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4011016