Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
1998-11-24
2001-06-12
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C714S030000, C714S045000
Reexamination Certificate
active
06247119
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to systems which have a processor with an instruction execution pipeline and, more particularly, to an apparatus for outputting information from an instruction execution pipeline in either an aligned or unaligned format.
BACKGROUND OF THE INVENTION
Processor architectures often separate the actions associated with executing an instruction into a plurality of successive stages. At a given point in time, several different instructions may be at respective different stages of execution. This technique, which is known as pipelining, increases the overall performance of the processor. However, pipelining can result in difficulty for a system developer who is attempting to debug the system, and who in particular is attempting to associate various signals in the pipeline to the instruction which performed them. This is because, at any given point in time, the pipeline includes various different signals which correspond to different instructions.
For example, a first stage of the pipeline may be handling a first instruction which is being decoded, a second stage may be handling a second instruction which is issuing an address for a memory read, a third stage may be handling a third instruction which is receiving data from a memory read, and a fourth stage may be handling a fourth instruction which is issuing an address and data for a memory write. Thus, as to any given instruction, it is not possible with the pipeline alone to observe, at a single point in time, all of the activity associated with execution of that instruction.
A known approach is to provide a flattener circuit, which buffers or delays selected pipeline signals until a later point in time. In particular, different signals from different pipeline stages are delayed by different amounts of time. The flattener simultaneously outputs all of the selected information for a given instruction, even though the information was gathered at different points in time during the execution of the instruction. While conventional flatteners of this type have been adequate for their intended purposes, they have not been satisfactory in all respects.
For example, where the processor and its pipeline are implemented in an integrated circuit, the flattener has been provided externally to the integrated circuit. Consequently, in order to have access to certain control signals of the pipeline, which normally would not be brought off the integrated circuit, a large number of external connection pins of the integrated circuit must be dedicated to pipeline signals, so that the external flattener can have access to the signals.
The number of external connection pins can be reduced slightly by providing off-chip circuitry to generate certain signals that are also generated within the integrated circuit, but such off-chip circuitry effectively duplicates circuitry within the integrated circuit, and thus increases the cost and power consumption of the overall system. A further consideration is that, in such systems, the flattener is remote from the source of pipeline activity, and thus may not be capable of operating at the speed of the processor when the processor is operating at higher frequencies, except through an approach which is sufficiently complex to be effectively cost-prohibitive.
SUMMARY OF THE INVENTION
From the foregoing, it may be.appreciated that a need has arisen for an apparatus which effects alignment of pipeline information while using a minimal number of external connection pins of an integrated circuit containing the pipeline, while avoiding duplicative circuitry, and while permitting the flattener to operate with the processor at higher speeds but without excessive cost.
According to the present invention, an integrated circuit is provided to address this need, and includes: a plurality of external connection pins; a processor which executes instructions from an instruction sequence, the processor including an instruction execution pipeline having a plurality of successive stages which correspond to respective successive phases of instruction execution, and the pipeline being operative to move instructions of the instruction sequence successively through the stages so that, at each of a plurality of successive points in time, each stage corresponds to a respective phase of execution of a respective instruction. The stages of the pipeline include a first stage, and a second stage immediately successive to the first stage. The integrated circuit includes a flattener register having an output which is coupled to a selected one of the external connection pins, and having an input which is coupled to a signal of the pipeline associated with the first stage. The integrated circuit is operative to cause the register to be loaded from the input thereof in association with an instruction being moved from the first stage to the second stage, so that when such instruction is in the second stage, the register maintains the state which the signal had when that instruction was in the first stage.
REFERENCES:
patent: 5751735 (1998-05-01), Tobin et al.
patent: 5838692 (1998-11-01), Tobin
patent: 5838897 (1998-11-01), Bluhm et al.
patent: 5867644 (1999-02-01), Ranson et al.
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6081885 (2000-06-01), Deao et al.
Brady W. James
Follansbee John A.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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