Coating processes – Centrifugal force utilized
Reexamination Certificate
2001-08-03
2004-02-10
Beck, Shrive P. (Department: 1762)
Coating processes
Centrifugal force utilized
C427S352000, C427S353000, C427S425000, C427S443200, C118S052000, C118S320000, C118S416000
Reexamination Certificate
active
06689418
ABSTRACT:
BACKGROUND OF THE INVENTION
Copper is becoming the conductor of choice for many integrated circuit manufacturers. Copper films exhibit better electromigration and stress-void resistance than aluminum, which was the primary conductor used by the semiconductor industry during the 1990's. The improved properties of copper enable manufacturers to reduce the RC time constant for circuits by either or both lowering the total resistance, R, of interconnect lines and decreasing the side-by-side capacitance of adjacent lines by decreasing the thickness of interconnect lines (i.e., reducing C while keeping R constant and carrying the same current in the smaller width line).
One method of forming a copper interconnect structure employs an electroplating process. In a typical copper electroplating process, a barrier layer of tantalum (Ta) or tantalum nitride (TaN) is first deposited over the substrate. Next, a seed layer, such as copper, is formed over the barrier layer. The copper seed layer can be formed using a variety of techniques including a chemical vapor deposition (CVD) process but is most often deposited using a physical vapor deposition (PVD) process. The substrate is then placed in a bath of an electrolyte plating solution and electric contact is made to the seed layer. Copper ions from the plating bath are attracted by the charge applied to the seed layer thereby forming a plated copper layer over the seed layer. After plating is completed, the substrate is typically transferred to a rinsing station where a solution of deionized water is applied to remove and neutralize any excess or remaining plating solution.
During the plating process, unwanted copper plating may occur on the edge and/or backside of the substrate. The extent of such unwanted plating depends in part on the formation of the seed layer. Some copper plating processes use a shadow mask or similar technique during deposition of the seed layer to exclude deposition from an outermost periphery, e.g., the outer 2 mm, of the substrate.
FIGS. 1A and 1B
show examples of plating processes that may result when deposition of the seed layer is excluded from the outer periphery of a substrate.
FIG. 1A
shows a cross-sectional view of a substrate
10
that has a front side
12
, a backside
14
and a beveled edge
16
between the front and backsides. In FIG.
1
A, a seed layer
20
, which stops short a distance A from beveled edge
16
, has been deposited over front side
12
of the substrate. During the plating process, a copper layer
22
is formed over seed layer
20
. Copper layer
22
forms only in portions of the substrate covered by seed layer
20
. Thus, depending on the distance A from edge
16
, copper layer
22
may form on edge
16
or may stop short of the edge as shown in FIG.
1
A. In
FIG. 1A
, however, an excess build-up of copper plating, shown as an edge bead
24
, forms at the edge of layer
22
. Edge bead
24
typically results from locally higher current densities at the edge of seed layer
20
and usually forms within 2-5 mm of edge
16
. Among other reasons, removal of edge bead
24
is generally desired to ensure uniform thickness of copper layer
22
on substrate
10
.
FIG. 1B
shows a cross-sectional view of another substrate
10
having similar front and backsides
12
and
14
and beveled edge
16
. As in
FIG. 1A
, a copper layer
22
is electroplated over a seed layer
20
that stops a short distance A from beveled edge
16
. Plated layer
22
includes a separated edge deposit
26
, however, rather than a beaded edge. Separated edge deposit
26
is susceptible to separating from the substrate during subsequent processing since it is not secured to the seed layer. Such a separation may abrade and damage the substrate during a CMP or other subsequent step. Accordingly, removal of separated edge deposit
26
is also generally desirable.
As part of the efforts to realize increased profits from integrated circuit manufacturing processes, the usable area of the substrate is being pushed to the limit. To this end, techniques that limit the use of the outer periphery of the substrate are disfavored by some semiconductor manufacturers. One technique that attempts to maximize the usable area of the substrate during copper electroplating is to use a full-coverage seed layer.
FIG. 1C
shows a cross-sectional view of a substrate
10
that has such a full-coverage seed layer. Substrate
10
in
FIG. 1C
has a front side
12
, a backside
14
and a beveled edge
16
between the front and backsides. A full-coverage seed layer
28
is deposited over the entire front side
12
as well as edge
16
and, sometimes, a small portion of backside
14
. During the plating process to form copper layer
30
, plating occurs on front side
12
, on edge
16
(shown as portion
34
) and possibly even on a small portion of backside
14
. Also, an edge bead
32
sometimes forms for reasons similar to those discussed above with respect to FIG.
1
A. Removal of portions
34
of layer
30
plated over edge
16
and/or backside
14
and bead
32
is generally desirable in order to limit contamination and particle problems that may otherwise result.
Accordingly, it can be seen that removing unwanted deposits from the edge and/or backside of the substrate is important to copper electroplating techniques. The industry has developed a number of different systems and techniques in order to accomplish the removal of such material. While some of these systems have been used quite successfully to remove unwanted material from the substrate's edge and/or backside, improved systems and techniques are still desirable.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an improved apparatus for and method of rinsing one side of a two-sided substrate and removing unwanted material from the substrate's edge and/or backside.
One embodiment of the method is directed toward rinsing and cleaning a substrate having a front side upon which integrated circuits are to be formed and a backside. This embodiment includes dropping the substrate front side down onto a pool of rinsing liquid in a manner such that the front side of the substrate is in contact with the solution while the substrate is held in suspension by the surface tension of the liquid thereby preventing the backside of the substrate from sinking under an upper surface of the pool. Next, while the substrate is in suspension in the rinsing liquid, the substrate is secured by its edge with a first set of fingers.
In another embodiment, a method of forming a copper layer on a front side of a substrate is disclosed. The method includes plating the copper layer over the front side of the substrate in a plating device and then transferring the substrate from the plating device to rinsing and cleaning station. At the rinsing and cleaning station, the substrate is dropped front side down onto a pool of rinsing liquid so that the surface tension of the liquid holds the substrate in suspension thereby preventing the backside of said substrate from sinking under an upper surface of the pool and then, while the substrate is suspended in the pool, it is secured by its edge with a first set of fingers.
In additional embodiments, after being secured by the first set of fingers the substrate is subsequently spun and a cleaning chemical is introduced to the backside of the substrate during a first time period. After the first time period, the substrate is secured by its edge with a second set of fingers and the first set of fingers is released. Additional cleaning chemical is then introduced to the backside of the substrate during a second time period. The cleaning chemical removes unwanted material from the substrate's edge and/or backside.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.
REFERENCES:
patent: 4840821 (1989-06-01), Miyazaki et al.
patent: 4903717 (1990-02-01), Sumnitsch
patent: 5130164 (1992-07-01), Hutchison et al.
p
Kholodenko Arnold V.
Mok Yeuk-Fai Edwin
Olgado Donald J. K.
Tepman Avi
Applied Materials Inc.
Beck Shrive P.
Jolley Kirsten Crockford
Townsend and Townsend and Crew
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