Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1998-12-09
2002-06-04
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S684000, C257S738000, C257S749000, C257S779000
Reexamination Certificate
active
06399958
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit device analysis, and more particularly to electrical trace inspection during device analysis for devices with solder ball attachments.
BACKGROUND OF THE INVENTION
With the advancements in semiconductor device technology, several different types of arrangements for integrated circuit devices have emerged. One arrangement involves the use of solder balls for attaching an integrated circuit device to a circuit board. Two examples of such devices are the fine-pitch ball grid array (FBGA) device and a micro ball grid array device (&mgr;BGA) device.
FIGS. 1 and 2
illustrate a partial cross-sectional diagram of a typical FBGA device and a typical &mgr;BGA device, respectively.
As shown in
FIG. 1
, an FBGA device
8
typically includes an integrated circuit die
10
encapsulated in packaging material
12
, e.g., an epoxy compound. Electrical connections for the die
10
are provided by bond wires
14
, such as gold wires, coupling input/output pads on the die
10
to bond pads
16
of a die paddle
18
, e.g., an elastomer material. The bond pads
16
electrically couple the die
10
to solder ball connectors
20
via traces
22
, e.g., copper tracings, in a tape material
24
, e.g., a polyimide tape. The solder ball connectors
20
capably attach the device
8
to a circuit board (not shown). As shown in
FIG. 2
, a &mgr;BGA device
30
includes an integrated circuit device
32
electrically coupled to solder balls
34
via bond wire
36
and trace
38
. The trace
38
is provided in a polyimide tape
40
. An elastomer seal layer
42
supports the coupling of the die
32
and bond wire
36
to the tape
40
.
While the advent of such devices attempts to overcome certain challenges facing circuit designers, the needs of device analysis for these devices are usually overlooked in the design process. In analyzing integrated circuit devices, such as those shown in
FIGS. 1 and 2
, part of the procedure is to visually inspect the traces and solder ball connections. Unfortunately, the small size and large number of the traces makes visual inspection a challenging process. Further hampering the visual inspection process is the polyimide tape in which the traces are secured. Normal polyimide tape is provided as colored material, e.g., usually blue or brown. Such coloring reduces the clarity of the visual inspection process, thus limiting the ability to perform desired device analysis fully.
Accordingly, a need exists for a manner of providing more successful visual inspection during device analysis. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides aspects for electrical trace inspection during device analysis for devices with solder ball attachments. In a method aspect, the method includes forming a desired integrated circuit device including bond wire attachments. The bond wire attachments are then utilized with electrical traces in a transparent tape layer, with visual inspection of the electrical traces performed through the transparent polyimide tape. In an apparatus aspect, the apparatus includes an integrated circuit die, the integrated circuit die including bond pads. The apparatus further includes bond wires coupled to the bond pads of the integrated circuit die, and a transparent tape layer, including a plurality of traces for electrically connecting to the bond wires, wherein visual inspection of the plurality of traces occurs through the transparent tape layer.
Through the present invention, more efficient and accurate device analysis occurs. The utilization of a transparent polyimide tape layer provides a straightforward technique of improving clarity during visual inspection of electrical traces in integrated circuit devices, such as FBGA and &mgr;BGA devices. The improvement in clarity further reduces the time needed to inspect the traces and offers more reliable viewing of the traces. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawing
REFERENCES:
patent: 4692387 (1987-09-01), Reich
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5205894 (1993-04-01), Ohta et al.
patent: 5470943 (1995-11-01), Sakata et al.
patent: 5601905 (1997-02-01), Watanabe et al.
patent: 5767528 (1998-06-01), Sumi et al.
patent: 5869887 (1999-02-01), Urushima
patent: 5872459 (1999-02-01), Pasiecznik, Jr.
patent: 5969088 (1999-10-01), Ezzell et al.
patent: 5986400 (1999-11-01), Staring et al.
patent: 6127729 (2000-10-01), Fukuda
patent: 709883 (1996-05-01), None
Advanced Micro Devices , Inc.
Chambliss Alonzo
Chaudhuri Olik
Sawyer Law Group LLP
LandOfFree
Apparatus for visual inspection during device analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for visual inspection during device analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for visual inspection during device analysis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2979323