Apparatus for using metastability-hardened storage circuits...

Details Apparatus for using metastability-hardened storage circuits... Apparatus for using metastability-hardened storage circuits...

2011-07-12

2011-07-12

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S027000

Reexamination Certificate

active

07977975

ABSTRACT:
An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

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Office Action from U.S. Appl. No. 12/568,567, dated Jun. 29, 2010, 8 pp.
J. Zhou et al., “A Robust Synchronizer,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'06), pp. 442-443, Mar. 2006.
U.S. Appl. No. 12/568,567, filed Sep. 28, 2009, Bruce B. Pederson.

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