Apparatus for use in a computer systems

Details Apparatus for use in a computer systems Apparatus for use in a computer systems

2004-04-20

2008-03-18

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S316000, C710S107000

Reexamination Certificate

active

07346722

ABSTRACT:
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.

REFERENCES:
patent: 4488232 (1984-12-01), Swaney et al.
patent: 4669079 (1987-05-01), Blum
patent: 4709364 (1987-11-01), Hasegawa et al.
patent: 5128926 (1992-07-01), Perlman et al.
patent: 5325495 (1994-06-01), McLellan
patent: 5375215 (1994-12-01), Hanawa et al.
patent: 5400334 (1995-03-01), Hayssen
patent: 5450547 (1995-09-01), Nguyen et al.
patent: 5481681 (1996-01-01), Gallo et al.
patent: 5541932 (1996-07-01), Nguyen et al.
patent: 5548733 (1996-08-01), Sarangdhar et al.
patent: 5555384 (1996-09-01), Roberts et al.
patent: 5619661 (1997-04-01), Crews et al.
patent: 5627976 (1997-05-01), McFarland et al.
patent: 5664117 (1997-09-01), Shah et al.
patent: 5754807 (1998-05-01), Lambrecht et al.
patent: 5912710 (1999-06-01), Fujimoto
patent: 5920894 (1999-07-01), Plog et al.
patent: 5925118 (1999-07-01), Revilla et al.
patent: 5986644 (1999-11-01), Herder et al.
patent: 6055228 (2000-04-01), DeKoning et al.
patent: 6057863 (2000-05-01), Olarig
patent: 6064679 (2000-05-01), Hashemi et al.
patent: 6232932 (2001-05-01), Thorner
patent: 0048869 (1982-04-01), None
patent: 0384621 (1990-08-01), None
patent: 08147163 (1996-06-01), None
patent: WO 80/01421 (1980-07-01), None
patent: WO 89/02127 (1989-03-01), None
Kim et al. “Hardware Synthesis for Stack type Partitioned-Bus Architecture”. Institute of Electrical and Electronics Engineers. 1999. CD5-01. 0-7803-5727-2/99.
Ewering. “Automatic Hich Level Synthesis of Partitioned Busses”. Institute of Electrical and Electronics Engineers. 1990. CH2924-9/90/0000/0304.
Frank et al. “Constrained Register Allocation in Bus Architectures”. Association for Computing Machinery. 1995. 32nd ACM/IEEE Design Automation Conference. 0-89791-756-1/95/0006.
“Universal Serial Bus Specification”, Revision 1.0. Jan. 15, 1996. pp. 2 and 27-31.
“IEEE Standard for a High Performance Serial Bus”, 1996. pp. i-ii and 31-35.

Affiliated with

Also associated with

Rating

Apparatus for use in a computer systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for use in a computer systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for use in a computer systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3960827