Apparatus for unaligned cache reads and methods therefor

Details Apparatus for unaligned cache reads and methods therefor Apparatus for unaligned cache reads and methods therefor

2005-07-05

2005-07-05

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S118000

Reexamination Certificate

active

06915385

ABSTRACT:
An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.

REFERENCES:
patent: 5557763 (1996-09-01), Senter et al.
patent: 6085289 (2000-07-01), Thatcher et al.
patent: 6112297 (2000-08-01), Ray et al.

Affiliated with

Also associated with

Rating

Apparatus for unaligned cache reads and methods therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for unaligned cache reads and methods therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for unaligned cache reads and methods therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3372808