Apparatus for translating digital signals

Details Apparatus for translating digital signals Apparatus for translating digital signals

1998-01-09

2002-06-11

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S056000

Reexamination Certificate

active

06404228

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates in general to digital signals and, more particularly to an apparatus for translating digital signals from one format to another format.
(b) Description of Related Art
Various types of digital signals and circuitry are used in industry. These signals and circuitry can be grouped into single-ended or differential formats. To convey one bit of information, single-ended signals require a single output that is referenced to ground. A typical example of a single-ended signal format includes a complimentary metal-oxide semiconductor (CMOS) signal format. Typical voltage values for CMOS signals are Vin
low
=0 V and Vin
high
=5 V. Alternatively, there is another format of CMOS circuitry referred to as NCMOS. NCMOS is an acronym for negative CMOS, a format identical to CMOS except that it operates on a negative voltage supply. The signals for NCMOS are typically Vin
low
=−5 V and Vin
high
=0 V. Another common form of single-ended signals is transistor-transistor logic (TTL). TTL signals range from Vin
low
=0.7 V to Vin
high
=3.5 V. CMOS, NCMOS, and TTL circuitry offer the advantages of low power consumption and high circuit density.
Differential digital signal formats include emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL). Differential signals generally include a true component and a false component. The true component is representative of the data bit to be conveyed, and the false component is the compliment of the data bit to be conveyed. Differential signals have meaning only when both components are examined together. Typical true and false voltage levels for ECL are Vin
low
=−1.8 V and Vin
high
=−1V. PECL true and false voltage levels are typically Vin
low
=3.5 V and Vin
high
=4.2 V.
When an ECL signal is “high” the true component will be approximately −1V and the false component will be approximately −1.8 V. Differential signals offer the advantage of high noise immunity.
Due to their distinct advantages, single-ended and differential signals, and their associated circuitry, are used in wide ranges of industrial applications. However, since the two signal formats are not readily compatible, it is not possible to connect a differential output directly to a single-ended NCMOS input. For example, it may be desirable to use differential signals (i.e., ECL or PECL) in an electromagnetically noisy environment such as a circuit board. However, most digital integrated circuits in use today are adapted to receive single-ended input signals, such as NCMOS signals. It is not possible to interface the differential signals directly to the single-ended inputs without the use of a translator circuit. Additionally, it is commonly known in industry to use both NCMOS and TTL signals. However, the two signal formats, although both single ended, are not compatible with one another due to voltage level differences.
Known translator circuits, such as Texas Instruments AM26LS32 and AM26LS33 differential line receivers, convert ECL or PECL signals to single-ended TTL outputs. However, these known translator circuits do not selectably translate both ECL and PECL to single-ended NCMOS signals, nor do they convert TTL signals to NCMOS signals.
SUMMARY OF THE INVENTION
The present invention is embodied in an apparatus for converting an input signal of a first format to an output signal of a second format. The converting apparatus includes an input level shifter that receives the input signal, wherein the input signal includes an emitter-coupled logic (ECL) signal, a positive emitter-coupled logic (PECL) signal, or a transistor-transistor logic (TTL) signal. The input level shifter is programmable by a selector input, wherein the selector input programs the input level shifter to shift the input signal to produce a differential signal. The apparatus further includes a secondary level shifter that converts the differential signal to a single-ended signal, along with an output buffer that converts the single-ended signal into a negative complimentary metal oxide semiconductor (NCMOS) signal, wherein the NCMOS signal is the output signal.
The invention itself, together with further objects and attendant advantages, will best be understood by reference to the following detailed description, taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5293081 (1994-03-01), Chiao et al.
patent: 5705940 (1998-01-01), Newman et al.
patent: 5877632 (1999-03-01), Goetting et al.
patent: 406132810 (1994-05-01), None

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