Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-10-12
2002-09-24
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S030000, C714S736000, C714S738000, C365S201000, C324S765010
Reexamination Certificate
active
06457148
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a multi-way interleave-type semiconductor device testing apparatus in which a plurality of test circuit units each having the same circuit configuration are provided and these test circuit units are operated in interleaved manner, thereby to permit the testing apparatus to test semiconductor devices at high speed.
BACKGROUND ART
FIG. 7
shows an example of the semiconductor device testing apparatus (hereinafter referred to as IC tester) for testing, for example, a semiconductor integrated circuit (hereinafter referred to IC) which is a typical example of the semiconductor devices. The illustrated IC tester TES comprises, mainly, a main controller
30
, a pattern generator
10
, a timing generator
31
, a waveform shaping device
32
, a waveform generator
33
, a group of drivers
1
, a group of level comparators
3
, a logical comparator
9
, a failure analysis memory
34
, and a device power supply
35
.
The main controller
30
is generally constructed by a computer system, and mainly controls the pattern generator
10
and the timing generator
31
in accordance with a test program PM created by a user. Although not shown, the timing generator
31
generally comprises a period generator, a clock control circuit, and a clock generator.
First, before a testing for ICs is started, various kinds of data are set in the IC tester from the main controller
30
. After the various kinds of data have been set, a testing for ICs is started. By a test start instruction or command applied to the pattern generator
10
from the main controller
30
, the pattern generator
10
starts to generate a pattern. Accordingly, the time point that the pattern generator
10
starts to generate a pattern becomes the time point of starting a testing. The pattern generator
10
supplies test pattern data to the waveform shaping device
32
and at the same time, supplies timing set information (which is also called timing set data) TS to a period generator and a clock generator, both of which are not shown, of the timing generator
31
.
The timing set information means a pair of one information for selecting period data previously set in a period data memory of the period generator and another information for selecting clock data previously set in a clock data memory of the clock generator. The timing set information is previously programmed by a user.
By application of the timing set information TS to the timing generator
31
, the timing generator
31
generates a timing signal (clock pulse) for controlling timings of operation of the waveform shaping device
32
, the logical comparator
9
and the like.
The test pattern data outputted from the pattern generator
10
in synchronism with the period data of the period generator is converted to a test pattern signal having a real waveform by the waveform shaping device
32
and the waveform generator
33
located at the succeeding stage of the waveform shaping device
32
. The test pattern signal is applied to an IC under test (commonly called DUT)
2
through a group of the drivers
1
to store it in the memory of the IC under test
2
.
On the other hand, a response signal read out of the IC under test
2
is compared in a group of the level (analog) comparators
3
with a reference voltage from a comparison reference voltage source (not shown) to determine whether or not the response signal has a predetermined logical level (a voltage of H logical level (high logical level), or a voltage of L logical level (low logical level)). A response signal which has been determined to have the predetermined logical level is sent to the logical comparator
9
where the response signal is compared with an expected value signal (data) outputted from the pattern generator
10
.
When the response signal does not coincide with the expected value signal, the memory cell of the IC under test
2
at the address thereof from which that response signal has been read out is determined to be defective or a failure, and a failure (FAIL) signal is generated indicating that the memory cell read out of the IC under test
2
is failure, and is stored in the failure analysis memory
34
. Usually, the failure signal is stored in a memory cell of the failure analysis memory
19
having the same address as that of the IC under test
20
.
On the contrary, when the response signal coincides with the expected value data, the memory cell of the IC under test at the address thereof from which that response signal has been read out is determined to be normal, and a pass signal indicating that the memory cell read out of the IC under test
2
is not defective is generated. Usually, this pass signal is not stored in the failure analysis memory
34
. At the time of completion of the test, the failure signals stored in the failure analysis memory
34
are read out thereof to determine, for example, whether the failure memory cell or cells of the tested IC
2
can be relieved or not.
As discussed above, the timing generator
31
generates, in accordance with the timing set information TS given from the pattern generator
10
, timing signals (clock pulses) for defining a rising timing and a falling timing of the waveform of a test pattern signal which is to be applied to an IC under test
2
, timing signals (clock pulses) for a strobe pulse defining a timing of the logical comparison in the logical comparator
9
, and the like.
Timings and periods for generating those timing signals are written as timing set information in the test program PM created by a user, and the IC tester is arranged such that a test pattern signal is applied to an IC under test
2
with an operating period or duty cycle and at a timing intended by a user to operate the IC under test
2
, and that whether the operation of the IC under test
2
is proper or not can be tested.
As shown in
FIG. 7
, a semiconductor device testing apparatus having one timing generator
31
, one pattern generator
10
, one waveform shaping device
32
, and one logical comparator
9
provided therein, and wherein a test pattern signal is generated using a timing signal (clock pulses) outputted from the one timing generator
31
to test the semiconductor device under test is called one-way system testing apparatus in this technical field.
On the contrary, a semiconductor device testing apparatus having a plurality of basic test circuit units provided therein, each basic test unit comprising one timing generator
31
, one pattern generator
10
, one waveform shaping device
32
, and one logical comparator
9
, and wherein timing signals (clock pulses) outputted from the timing generators of the plurality of basic test circuit units are multiplexed, and the plurality of basic test circuit units are operated in interleaved manner using the multiplexed timing signals to generate a test pattern signal, thereby to test a semiconductor device under test is called a multi-way interleave-type testing apparatus in this technical field (the interleave operation of the plurality of basic test circuit units means that the plurality of basic test circuit units are sequentially operated within one cycle (one period) at timings shifted a little by a little from one another, that is, the plurality of basic test circuit units are operated in parallel manner within one cycle).
A semiconductor memory having a clock synchronous type interface (a device of synchronous type) such as a synchronous DRAM (a synchronous dynamic RAM) has a function for delaying an output cycle of data therein, and by setting the number of cycles to be delayed in a register within the memory, the memory can output an input data thereinto with a delay corresponding to the number of cycles set in the register. The number of cycles to be delayed is called latency in this technical field.
In case of testing such a synchronous type device in a semiconductor device testing apparatus, it is necessary to delay an expected value signal (EXP) and a comparison enable signal (CPE) outputted from a pattern generator by a latency set in the device under t
Advantest Corporation
Gallagher & Lathrop
Lathrop, Esq. David N.
Moise Emmanuel L.
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