Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2002-04-01
2004-02-17
Le, N. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S501000, C324S763010, C257S084000
Reexamination Certificate
active
06693446
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-44450, filed on Jul. 24, 2001, the contents of which are herein incorporated by reference in their entirety.
Field of the Invention
The present invention relates to an apparatus of testing an integrated circuit interconnection. More particularly, the present invention relates to a test apparatus which is suitable for testing a leakage protection reliability of an integrated circuit interconnection having a high via density.
BACKGROUND OF THE INVENTION
As semiconductor devices become highly integrated, sizes of individual devices and wires or interconnections become smaller. As one method of highly integrating the semiconductor devices, semiconductor devices may be formed to have three-dimensional structures. For example, interconnections of connecting semiconductor devices are formed over multiple layers to have three-dimensional structure in the semiconductor devices.
With reference to the multilayered interconnection, it is very difficult to form many semiconductor cells and to connect these cells one another for fabricating a circuit. Very crowded and complicated interconnections are formed in one layer. But, when the interconnections are complicated, it is almost impossible to connect all circuits in one layer. In order to resolve this difficulty and to increase the efficiency, first, a lower interconnection is formed, secondly, an interlayer dielectric layer is formed, and thirdly, an upper interconnection is formed. A contact hole is formed at the interlayer dielectric layer and a plug fills the contact hole to connect the upper interconnection with the lower interconnection, thereby forming a circuit. As the circuit becomes complicated, the number of the layers used in multilayered interconnection continuously increases.
When a circuit is designed according to a certain design rule, a test for reliability of an interconnection is performed. In the test, it is possible to test whether a gap between patterns is too narrow and a potential difference between patterns is too high. Also, for the test, a weak point where an electric field is concentrated is artificially fabricated, and a maximum voltage or a maximum current is applied thereto. In order to increase the efficiency of the test, a minimum interconnection part of the designed circuit is composed of a plurality of repeated patterns, a certain voltage is applied to each opposite patterns in repeated pattern pairs. The form of the pattern may not be identical with the real thing, but be simplified and fixed. As an important method of testing the leakage protection reliability, a standard comb—comb-like (hereinafter, simply comb—comb) pattern or comb-serpentine (hereinafter, simply comb-serpentine) pattern is used.
However, this method is used for evaluating a leakage protection reliability between interconnections in one layer. That is, in an initial step of fabricating an integrated circuit, a contact or a via connecting different layers has a lower density than the density of an interconnection formed in one layer. Additionally, when a via or a contact is required, it is possible to form it at a relatively untroubled point i.e. an area of relatively low circuit density. Thus, a conventional apparatus of testing an integrated circuit is for detecting a problem between narrow interconnections in one layer rather than a problem of a via or a contact connecting between layers.
FIG. 1
illustrates an apparatus of testing a comb-serpentine pattern, which is a typical example of a conventional apparatus of testing an integrated circuit.
Referring to
FIG. 1
, one comb pattern
10
or
20
has one length portion and multiple tooth portions extending orthogonally from the length portion at the same level with the length portion. The tooth portions are orthogonal to the length portion, parallel with one another and repeated, thereby having the same length. In a test apparatus, a pair of comb patterns
10
and
20
are aligned with facing each other, and the tooth portions of one comb pattern are running between other tooth portions of the other comb pattern. A serpentine pattern
30
is present between the pair of the comb pattern. Between the pair of the comb patterns, the serpentine-like pattern
30
passes parallel with the tooth portions between two tooth portions and turns vertically at a region between the length portion of one comb pattern and the end of the tooth portion of the other comb pattern. A maximum electric field
40
is localized at a region adjacent to the ends of the tooth portion and the neighboring serpentine pattern. Since the maximum electric field
40
is localized at the every end of the tooth portions, there are plural instances of maximum electric field
40
. When a leakage or a short is not generated at the every maximum electric field
40
, the design of a semiconductor device exhibits stability and reliability.
A form of apparatus for testing a leakage or a short generated between interconnection layers is shown in FIG.
2
. In the form, two conductive layers
50
and
60
are formed and one interlayer dielectric layer
70
is interposed therebetween. Potential difference is applied through two electrodes
80
connected with each conductive layer. But, the form is too simplified to find a real-world problem related to a via or a contact according to a multilayered interconnection of a semiconductor device. Thus, in case that a via or a contact is substantially troubled in a relatively simple semiconductor device having few vias or contacts, the trouble is caught by an experiential method of trial and error.
As semiconductor devices become extremely highly integrated, and interconnections become multilayered, the density of vias or contacts increases. A short or a leakage current may be frequently generated between vias. However, in a highly integrated semiconductor device, a small difference in process conditions may result in a considerable difference in results or effects. For example, in case of using a different method of forming a via hole and filling the via hole with a conductive material, or in case of using a different conductive material, a formed via may have a different characteristic with respect to the leakage current or the short.
For more specific examples, in an integrated semiconductor device, copper is used for an interconnection and a via to reduce resistance of an interconnection or a contact. But, when the copper is processed, the processed surface of copper or copper oxide tends to be rough. Thus, using the copper may substantially result in the narrow interconnection gap due to the rough surface or other irregularity thereof and result in strong possibility of failure, in comparison with other interconnection metal having the same interconnection gap.
Additionally, when the copper is used, a dual damascene process is generally employed because of difficulty in patterning. When an aspect ratio of the via hole is increased, a barrier layer is formed at the surface of the via hole by employing a sputtering method before filling the via hole with metal interconnection. But, the barrier layer is not well stacked at an edge where the sidewall and the low surface of the via hole are connected, and thus, the copper of high conductivity may contact at a neighboring silicon oxide layer. A leakage or an insulation breakdown may be more frequently created at the bottom of the via than at other regions.
The leakage or the short may result from various causes. If there are a lot of spots having strong possibilities of failure like the leakage current or the short circuit, it is difficult to find out the failed spots and to revise them. Thus, without a systematic test, it is difficult to know whether a leakage or a short may be generated between vias in a semiconductor device. Consequently, a systematic and operational method is required also to detect the failed spots between vias or contacts. In order to realize the method, a test apparatus having a specific pattern is required, in which
Kim Jung-Woo
Kim Sam-Young
Lee Chang-Sub
Park Ki-Chul
Song Won-Sang
Le N.
Marger & Johnson & McCollom, P.C.
Nguyen Vincent Q.
Samsung Electronics Co,. Ltd.
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