Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-08-18
1999-11-02
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 371 101, G11C 700
Patent
active
059782897
ABSTRACT:
During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit address is compressed to 9-bits, freeing up 2 bits). Redundant element enable circuitry is coupled to one or more pins on a packaged chip that are unused during the compression mode testing. The circuitry receives control signals from external testing circuitry to select between the primary memory array in the chip, and redundant rows and columns of memory in the chip. As a result, during compressed address mode testing of the chip, a full 11-bit word is input to test the circuitry, but where 2 of the 11 bits allow the external circuitry to toggle between, and thereby selectively access, the rows and columns of primary and redundant memory in the chip. Alternatively, the circuitry can also be coupled to a non-connected pin on the packaged chip so as to operate during a non-compression mode testing.
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Micro)n Technology, Inc.
Nguyen Viet Q.
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