Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1999-01-07
2000-09-12
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, G11C 700
Patent
active
061187119
ABSTRACT:
During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit address is compressed to 9-bits, freeing up 2 bits). Redundant element enable circuitry is coupled to one or more pins on a packaged chip that are unused during the compression mode testing. The circuitry receives control signals from external testing circuitry to select between the primary memory array in the chip, and redundant rows and columns of memory in the chip. As a result, during compressed address mode testing of the chip, a full 11-bit word is input to test the circuitry, but where 2 of the 11 bits allow the external circuitry to toggle between, and thereby selectively access, the rows and columns of primary and redundant memory in the chip. Alternatively, the circuitry can also be coupled to a non-connected pin on the packaged chip so as to operate during a non-compression mode testing.
REFERENCES:
patent: 4573146 (1986-02-01), Graham et al.
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 5124949 (1992-06-01), Morigami
patent: 5134587 (1992-07-01), Steele
patent: 5212442 (1993-05-01), O'Toole et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5295102 (1994-03-01), McClure
patent: 5319599 (1994-06-01), Kato
patent: 5355338 (1994-10-01), Han
patent: 5355340 (1994-10-01), Coker et al.
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5434438 (1995-07-01), Kuo
patent: 5455798 (1995-10-01), McClure
patent: 5466888 (1995-11-01), Beng et al.
patent: 5469401 (1995-11-01), Gillingham
patent: 5491664 (1996-02-01), Phelan
patent: 5511029 (1996-04-01), Sawada et al.
patent: 5528539 (1996-06-01), Ong et al.
patent: 5535161 (1996-07-01), Kato
patent: 5544106 (1996-08-01), Koike
patent: 5559741 (1996-09-01), Sobue
patent: 5563832 (1996-10-01), Kagami
patent: 5574729 (1996-11-01), Kinoshita et al.
patent: 5577050 (1996-11-01), Bair et al.
patent: 5590075 (1996-12-01), Mazzali
patent: 5602786 (1997-02-01), Pascucci et al.
patent: 5612918 (1997-03-01), McClure
patent: 5617365 (1997-04-01), Horiguchi et al.
patent: 5619462 (1997-04-01), McClure
patent: 5652725 (1997-07-01), Suma et al.
patent: 5659509 (1997-08-01), Golla et al.
patent: 5680354 (1997-10-01), Kawagoe
patent: 5691945 (1997-11-01), Liou et al.
patent: 5708619 (1998-01-01), Gillingham
patent: 5781486 (1998-07-01), Meritt
patent: 5790462 (1998-08-01), McClure
patent: 5809225 (1998-09-01), Ohsawa et al.
Micro)n Technology, Inc.
Nguyen Viet Q.
LandOfFree
Apparatus for testing redundant elements in a packaged semicondu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for testing redundant elements in a packaged semicondu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for testing redundant elements in a packaged semicondu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-102062