Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-01-24
2001-07-03
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S710000, C714S711000, C714S742000
Reexamination Certificate
active
06256757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to memories having spare rows and columns of memory cells that can be used to replace rows and columns having defective cells, and in particular to an apparatus for testing such a memory and generating data for facilitating allocation of spare rows and columns.
2. Description of Related Art
A typical random access memory (RAM) includes an array of rows and columns of memory cells, each cell having a unique combination of row and column address. Many RAMs include redundant storage elements in the form of spare rows and columns of memory cells. When such a RAM is found to have a defective memory cell, a row or column containing that memory cell can be replaced with one of the RAM's spare rows or columns. The replacement is accomplished by using a laser or other means to alter the RAM so that the spare row or column is addressed in lieu of the row or column containing the defective cell.
When such a RAM has a defective cell it can be repaired by replacing either its row or column with a spare row or column. However it is important to allocate spare rows and columns efficiently. For example assume a RAM has one spare row and three spare columns. Assume also that the RAM has 6 defective cells with three of them occurring in its first row. If we replace the first row with the spare row, then we can use the three spare columns to replace columns containing the three defective cells that are not in the first row. However if we use the three spare columns to replace the columns containing the three cells in the first row, we may not have enough remaining spare rows and columns to replace the three cells that are not in the first row.
Prior art memory testers typically test each memory cell of a RAM device under test (DUT) by writing data to the memory cell and then reading the data back out to determine whether the data read out matches the data written into the cell. A high speed memory tester employs a pattern generator or counters to produce the data, address and control signals needed to write data into the memory cells and read it back out. A hardware comparator typically compares the memory input and output data and supplies data indicating the result of the comparison to an “error capture memory” having one storage memory for each memory cell to store the results of the comparison. After each memory cell of the DUT has been tested, the contents of the error capture memory constitutes a bit map of the DUT, with each bit indicating whether a corresponding memory cell of the DUT is defective. Following the test, a host computer reads the contents of the error capture memory and determines therefrom how best to allocate spare rows and columns when replacing the defective memory cells.
One problem with this system is that since the error capture memory has to have as many cells as the memory being tested, and since memories can be quite large, it takes a relatively long time for the host computer to read all of the data out of the error capture memory. In a production environment where thousands of memories are being tested in succession, the total time the host computer requires to read the captured error data is substantial and comprises a significant portion of the time required to test the memories.
Thus it would be beneficial to provide a memory test system that can quickly test a memory and quickly provide a host computer with a relatively small amount of data that will enable the host computer to determine how to allocate spare rows and columns, and which does not require the host computer to read the entire contents of an error capture memory.
SUMMARY OF THE INVENTION
A memory tester in accordance with the invention quickly tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and quickly provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells.
During a test the memory tester tests each memory cell of the DUT and writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective.
In accordance with one aspect of the invention, the tester also counts of the number of defective memory cells in each row and column. After the test the count for each row and column is supplied to the host computer. In many cases, the host computer will be able to determine how to allocate spare rows and columns to replace DUT rows and columns containing defective memory cells on the basis of the count data alone.
In accordance with another aspect of the invention, in cases where the host computer is unable to determine how to allocate the spare rows and columns from the count data alone, it requests the tester to process the data in the ECM to determine and supply the host computer with particular addresses of the defective memory cells. The host computer is then able to determine how to allocate spare rows and columns on the basis of this address data.
The memory tester in accordance with the invention provides the necessary information to the host computer more quickly than typical prior art testers because it presents the information in a compact form and because it does not require a host computer to directly read access every storage location in the ECM to determine which cells are defective. In most cases the test process ends after the host computer acquires the relatively small amount of row and column error count data because the host computer will be able to determine a suitable allocation for spare rows and columns based solely on that data. Even when the host computer cannot determine how to allocate spare rows and column on the basis of the count data, it does not read and process the contents of the ECM. This is done by hardware within tester which can do so more quickly. Moreover, not all storage locations in the ECM are read. In accordance with a further aspect of the invention, the tester reads and processes data from only the rows (or columns) of the ECM that correspond to rows or columns of DUT containing defective cells.
It is accordingly an object of the invention to quickly test a memory having spare rows and columns and to quickly provide a host computer with a small amount of data that is sufficient to enable it to determine how to efficiently allocate spare rows and columns to replace rows and columns containing defective memory cells.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
REFERENCES:
patent: 4833652 (1989-05-01), Isobe et al.
patent: 5481550 (1996-01-01), Garcia et al.
patent: 5495447 (1996-02-01), Butler et al.
patent: 5795797 (1998-08-01), Chester et al.
patent: 6065141 (2000-05-01), Kitagawa
patent: 6072737 (2000-06-01), Morgan et al.
Bedell Daniel J.
Credence Systems Corporation
Moise Emmanuel L.
Smith-Hill and Bedell
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