Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-04-12
2011-04-12
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S726000
Reexamination Certificate
active
07925937
ABSTRACT:
An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
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Constant Gregory A.
Dankert Floyd L.
Giles Grady L.
Irby Joel T.
Novak Amy M.
Advanced Micro Devices , Inc.
Britt Cynthia
Heter Erik A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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