Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-07-13
2003-09-30
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S104000, C713S401000, C365S193000, C365S194000
Reexamination Certificate
active
06629222
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory interface that automatically adjusts the timing between read data and an associated strobe signal returning from a memory during a read operation. The present invention also adjusts timing between the read data and an input driver enable signal.
2. Related Art
As processor speeds continue to increase, memory systems are under increasing pressure to provide data at faster rates. This has recently led to the development of new memory system designs. Memory latencies have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory chip in a continuous stream. Such memory chips with clocked interfaces are known as synchronous random access memories.
Recently, standards such as SyncLink and DDR have been developed to govern the transfer of data between memory and processor using such clocked interfaces.
SyncLink, which will be known as IEEE Standard 1596.7, specifies an architecture that supports a 64M-bit memory with a data transfer rate of 1.6 gigabytes per second.
DDR is an acronym for Double Data Rate SDRAM; SDRAM is an acronym for Synchronous Dynamic Random Access Memory. During read operations, DDR memories return a bi-directional data strobe signal (or data clock signal) along with the data. The data is clocked into the processor (or memory controller) on both edges of the data strobe signal. This differs from conventional memory systems, which rely on the system clock to latch the data received during a read operation.
Designing an interface that receives a data strobe signal from a DDR memory during a read operation presents challenges because a certain amount of skew typically arises between the data signal and the data strobe signal. If this skew is large enough, a data strobe edge, which is used to latch the data signal, can move from the center of the “data eye” of the data signal into a transitional region or into another data eye. This may cause spurious data to be latched during a read operation. Skew may additionally arise between the data signal and an enable signal for an input driver that is used to drive the data signal from a memory bus into a latch in the processor (or in the memory controller). This type of skew may also cause spurious data to be latched during read operations.
What is needed is a system that adjusts the temporal alignment between a data signal and an associated data strobe signal received from a memory during a read operation. Additionally, what is needed is a system that adjusts the temporal alignment between a data signal received during a read operation and an associated input driver enable signal.
SUMMARY
One embodiment of the present invention provides an apparatus that synchronizes a data signal and a data strobe signal received from a random access memory. This apparatus includes a mechanism that initiates a read operation to the random access memory by sending a target address for the read operation to the random access memory. The apparatus also includes an input driver that receives the data signal containing data retrieved from the target address from the random access memory. Coupled to the input driver is a register that stores the data signal. A first programmable delay circuit is coupled to an enable input of the input driver in order to synchronize the driving of the input driver with the data signal received from the random access memory. A second programmable delay circuit is coupled between the data strobe signal and a clock input of the register. This second programmable delay circuit is configured to delay the data strobe signal so as to synchronize the data strobe signal with the data signal received from the random access memory.
One embodiment of the present invention includes a mechanism to program the first programmable delay circuit with a first delay value, and a mechanism to program the second programmable delay circuit with a second delay value.
One embodiment of the present invention includes an initialization mechanism that determines the first delay value and the second delay value by performing test read operations using a plurality of different combinations of different first delay values and different second delay values. In a variation on this embodiment, this initialization mechanism includes code executed during a system boot process that determines the first delay value and the second delay value.
In one embodiment of the present invention, the first programmable delay circuit includes a coarse delay adjustment mechanism and a fine delay adjustment mechanism.
One embodiment of the present invention includes a circuit that de-asserts the enable signal a fixed amount of time after the enable signal is asserted.
One embodiment of the present invention includes a circuit that de-asserts the enable signal a programmable amount of time after the enable signal is asserted.
In one embodiment of the present invention, the random access memory is comprised of a plurality of memory modules, wherein a different first delay value and a different second delay value are associated with each memory module. This embodiment further includes a mechanism that examines the target address to determine which memory module the target address is directed to in order to determine an associated first delay value and an associated second delay value for the memory module.
One embodiment of the present invention includes a re-calibration mechanism that periodically measures deviations in propagation delay through the first programmable delay circuit and/or the second programmable delay circuit relative to a system clock, and adjusts the first programmable delay circuit and/or the second programmable delay circuit, if necessary, to compensate for measured deviations.
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Bragdon Reginald G.
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
Vital Pierre M.
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