Patent
1985-06-21
1987-06-23
Miller, Stanley D.
328 55, H03L 700
Patent
active
046756124
ABSTRACT:
Disclosed is an apparatus for synchronizing a first signal with a second signal comprising a plurality of delay means D.sub.i as i goes from 1 to N, where N is an integer, each delay means D.sub.i having an input I.sub.i and a delay output O.sub.i for delaying a signal received at the respective input I.sub.i by an increment .delta.t of time in supplying the delayed signal at the respective delay output O.sub.i. The first delay means D.sub.1 of the plurality of delay means is connected to receive the first signal at its input I.sub.1. Each of the other delay means D.sub.i, for i equal to 2 to N, are connected in series such that the respective input I.sub.i is connected to receive the delay output O.sub.i-1 of the preceding delay means D.sub.i-1. A plurality of latch means L.sub.i, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L.sub.i latches the signal at the delay output O.sub. i respectively for each of the delay means D.sub.i, in response to the second signal and supplies the latched signal at a respective latch output Q.sub.i. Output logic means, responsive to at least a subset of the plurality of delay outputs O.sub.i and plurality of latch outputs Q.sub.i, for supplying essentially a phase-shifted copy of the first signal synchronized with the second signal is provided.
REFERENCES:
patent: 3502991 (1970-03-01), Sampson
patent: 3588707 (1971-06-01), Manship
patent: 4011516 (1977-03-01), Heimbigner
patent: 4023110 (1977-05-01), Oliver
patent: 4386323 (1983-05-01), Jansen
Adams Neil R.
Clapp Craig S. K.
Advanced Micro Devices , Inc.
Haynes Mark A.
King Patrick T.
Miller Stanley D.
Ohralik K.
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