Apparatus for suppressing ghosts in signals modulating a carrier

Television – Image signal processing circuitry specific to television – Noise or undesired signal reduction

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348607, H04N 521

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active

055327559

ABSTRACT:
Composite video signal and a relatively low power phase-shift-keyed (PSK) signal encoding digital information are transmitted on respective phases of a video carrier in quadrature with each other. Selected scan lines of the composite video signal contain ghost-cancellation reference (GCR) signals. A digital signal receiver performs a first detection of the video carrier modulated in the two phases, down-converting to an intermediate-frequency (IF) signal. This IF signal is selectively amplified prior to respective second detection of the down-converted video carrier by in-phase and quadrature-phase synchronous video detectors. A first cascade filter connection of a first ghost-cancellation filter and a first equalization filter follows the in-phase video detector, and a second cascade filter connection of a second ghost-cancellation filter and a second equalization filter follows the quadrature-phase video detector. Gating circuitry selects scan lines containing GCR signals from the video signal response of the first cascade filter connection for accumulation, which generates separated ghosted GCR signal for use by a computer such as a microcomputer. Adjustable parameters of the ghost-cancellation filters are adjusted in parallel responsive to computer calculations, while adjustable parameters of the equalization filters are also adjusted in parallel responsive to further computer calculations. Iterative feedback reduces ghosts in the response of the first cascade filter connection. Ghosts in the response of the second cascade filter connection are reduced in an analogous manner.

REFERENCES:
patent: 5177611 (1993-01-01), Gibson et al.
patent: 5276507 (1994-01-01), Uwabata et al.
patent: 5331416 (1994-07-01), Patel et al.
T. C. Leslie and B. Singh, "An Improved Sigma-Delta Modulator Architecture", 1990 IEEE Symposium on Circuits & Systems, 90 CH 2868-8900000-0372, pp. 372-375.

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