Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-07-13
2002-05-07
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000
Reexamination Certificate
active
06385686
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the design of computer system buses for transferring data between computer system components. More specifically, the present invention relates to a system that supports multiple delayed read transactions between computer buses.
2. Related Art
In order to improve computer system performance, some processors, such as the Intel Pentium, are designed to drive an additional request across a computer system bus before the current bus request is completed. This technique is known as “bus pipelining.” (The Intel Pentium is manufactured by the Intel Corporation of Santa Clara, Calif.)
Bus pipelining improves computer system performance because more than one bus transaction can be processed at the same time. However, this performance advantage can be lost when both requests are read operations directed from a processor bus, such as the Pentium Processor Bus, to a peripheral bus, such as the PCI bus. This is due to the fact that on certain peripheral buses, such as the PCI bus, a bus master can send a retry command back to the processor if the current request is delayed or cannot otherwise be completed immediately. When such a retry command is received by a processor bus, such as the Pentium Processor Bus, the retry command causes both the current request and the pipelined request to be terminated and re-attempted by the processor. (The term “Pentium Processor Bus” as used in this specification refers to a bus adhering to the protocol described in Volume 1 of the “The Pentium Family Developer's Manual,” published in 1995 by the Intel Corporation.)
Consequently, in order to maintain ordering of transactions on the processor bus, the pipelined read request cannot be given to the peripheral bus until the current read request is guaranteed to complete. This removes the performance advantage of pipelining.
What is needed is a system that allows a pipelined read request to proceed in parallel with a current read request on a peripheral bus in spite of the fact that a retry on a processor bus causes all requests on the processor bus to be terminated and retried.
SUMMARY
One embodiment of the present invention provides a system that supports multiple delayed read transactions. The system includes a host bus and a peripheral bus. The system also includes a receiving mechanism that is configured to receive a first request and a pipelined request that originate from the host bus and are directed to the peripheral bus. The first request and the pipelined request are stored in a first buffer and a second buffer. The system additionally includes a sending mechanism that is configured to send the first request to the peripheral bus, so that the first request is processed when the peripheral bus becomes available. If the pipelined request is received and if the pipelined request is a read operation, the sending mechanism is configured to send the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available. The system also includes a retry mechanism that issues a retry request across the host bus that causes both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions.
In one embodiment of the present invention, the system additionally includes a data returning mechanism that returns the read data across the host bus in the case where the first request is a read operation that was previously requested and the read data has been returned by the peripheral bus.
In one embodiment of the present invention, the receiving mechanism is configured to wait a predetermined amount of time for the pipelined request. In a variation on this embodiment, the receiving mechanism includes a programmable counter that contains the predetermined amount of time.
One embodiment of the present invention includes a host bridge that couples together the host bus and the peripheral bus, wherein the receiving mechanism, the sending mechanism, the retry mechanism the first buffer and the second buffer are located on the host bridge. In a variation on this embodiment, the host bridge includes a host slave module that acts as a slave device on the host bus, and a peripheral master module that acts as a master device on the peripheral bus.
In one embodiment of the present invention, the receiving mechanism is configured to receive a programmable delay enable signal that enables delayed read operations.
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Lefkowitz Sumati
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
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