Apparatus for superscalar instruction pre-decoding using cached

Details Apparatus for superscalar instruction pre-decoding using cached Apparatus for superscalar instruction pre-decoding using cached

1996-04-29

1998-11-03

Lall, Parshotam S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711137, G06F 930

Patent

active

058322590

ABSTRACT:
In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instructions. A branch prediction cache stores the target instruction and next sequential instruction, and is tagged by the address of the branch instruction, as in the prior art. In addition, however, the branch prediction cache also stores the length of the first and second instructions and the address of the second instruction. This additional data allows the target and next sequential instructions to be directly aligned and presented to the parallel decoding circuits without waiting for a calculation of their lengths and starting addresses.

REFERENCES:
patent: 4764861 (1988-08-01), Shibuya
patent: 4777587 (1988-10-01), Case et al.
patent: 4853889 (1989-08-01), Ditzel et al.
patent: 4860197 (1989-08-01), Langendorf et al.
patent: 4984154 (1991-01-01), Hanatani et al.
patent: 5093778 (1992-03-01), Favor et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5142634 (1992-08-01), Fite et al.
patent: 5163140 (1992-11-01), Stiles et al.
patent: 5168571 (1992-12-01), Hoover et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5327547 (1994-07-01), Stiles et al.
patent: 5353421 (1994-10-01), Emma et al.
patent: 5394529 (1995-02-01), Brown et al.
patent: 5442756 (1995-08-01), Grochowski et al.
patent: 5448746 (1995-09-01), Eickemeyer et al.
patent: 5450605 (1995-09-01), Grochowski et al.
patent: 5485587 (1996-01-01), Matsuo et al.
patent: 5500942 (1996-03-01), Eickemeyer et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.
patent: 5504932 (1996-04-01), Vassiliadis et al.
patent: 5515518 (1996-05-01), Stiles et al.
patent: 5522053 (1996-05-01), Yoshida et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5535347 (1996-07-01), Grochowski et al.
patent: 5537629 (1996-07-01), Brown et al.
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5559974 (1996-09-01), Boggs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5574871 (1996-11-01), Hoyt et al.
patent: 5574873 (1996-11-01), Davidian
patent: 5581717 (1996-12-01), Boggs et al.
Anderson, D. et al., Pentium Processor System Architecture, (1993) pp. 144-145, 159-160.

Affiliated with

Also associated with

Rating

Apparatus for superscalar instruction pre-decoding using cached does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for superscalar instruction pre-decoding using cached , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for superscalar instruction pre-decoding using cached will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-701613