Apparatus for statistical LSI delay simulation

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing

Reexamination Certificate

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Details

C703S013000, C703S014000, C703S015000, C703S016000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10756471

ABSTRACT:
A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

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