Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-10-28
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189110, C365S185210, C365S207000, C365S189050
Reexamination Certificate
active
06243314
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to an apparatus for sensing a current direction of an input signal and amplifying the sensed input signal to a logic level in use for semiconductor memory devices, in which an erroneous operation can be prevented and a data access time therein is improved.
DESCRIPTION OF THE PRIOR ART
As is well known to those skilled in the art, a sense amplifier serves as an amplifying device with a high gain and a wide band, which is use to amplify signals read out from memory cells to output the amplified signals as a logic level. The typical sense amplifiers sense a voltage level of an input signal and amplify the sensed input signal to output the amplified signal as a logic level.
FIG. 1
is a schematic diagram illustrating a SRAM (static random access memory) having a conventional sense amplifier.
Referring to
FIG. 1
, a memory cell
100
stores data. A bit line pair transfer the data stored in the memory call
100
. The bit line pair include a bit line BL
0
and a complementary bit line/BL
0
, wherein the bit line pair are respectively held at different voltage level. For example, when the bit line BL
0
is held at a high level, the complimentary bit line/BL
0
is held at a low level. A first switching transfer MS
1
, connected between the bit line BL
0
and the memory cell
100
, is switched in response to a write word line signal WWL which is activated by a write address. A second switching transistor MS
2
, connected between the memory cell
100
and the complementary bit line/BL
0
, is switched in response to the write word signal WWL. A third switching transistor MS
3
, one of whose terminals is connected to a read bit line RBL
0
, is switched in response to a read word line signal RWL which is activated by a read address. A fourth switching transistor MS
4
receives the stored data from the memory cell
100
, one of whose terminals is connected to the other terminal of the third switching transistor MS
3
and the other terminal is connected to a ground voltage level. A first PMOS transistor MP
1
supplies a precharge voltage, i.e., a power supply voltage level, to the read bit line RBL
0
in response to a precharge signal PS. A fifth switching transistor MS
5
is switched in response to a column select signal CS to transfer a read data, wherein the read data is a signal transferred from the memory cell
100
to the read bit line RBL
0
through the third and fourth switching transistors MS
3
and MS
4
. A sense amplifier
120
, connected to the fifth switching transistor MS
5
, senses and amplifies the read data to output the amplified read data. A second PMOS transistor MP
2
, connected between the power supply voltage level VDD and an input terminal of the sense amplifier
120
, charges the input terminal of the sense amplifier
120
to the power supply voltage in response to the amplified read data.
A read/write operation of the SRAM having the sense amplifier will be described with conjunction to FIG.
1
.
At write operation, the first and second switching transistors MS
1
and MS
2
are turned on in response to the write word line address WWL, wherein the write word line signal WWL is enabled in response to the write address signal. Then, data on the bit line BL
0
and the complementary bit line/BL
0
are stored to the memory cell
100
through the turned-on first and second switching transistors MS
1
and MS
2
. At this time, the memory cell
100
is implemented with a form of inverter latch, so that the stored data can be continuously retained in the memory cell
100
until the power supply voltage is removed.
On the other hand, at read operation, the third switching transistor MS
3
is turned on in response to the read word line signal RWL, wherein the read word line signal RWL is enabled by a read address signal. At this time, if the data stored in the memory cell
100
is “high”, the fourth switching transistor MS
4
is turned on, so that a voltage level on the read bit line RBL
0
is pulled down from the precharge potential (power supply voltage level) to a “low” level. If the data stored in the memory cell
100
is “low”, the fourth switching transistor MS
4
is turned off, so that the read bit line RBL
0
keeps the precharge potential. Then, the voltage level on the read bit line RBL
0
is transferred to the sense amplifier
120
through the fifth switching transistor MS
5
. The sense amplifier
120
then amplifies the transferred voltage level to output the amplified voltage of a logic level as the read data.
As a capacity of the SRAM becomes increasing through sophisticated technology, the number of memory cells connected to the read bit line is also increased, resulting in an increase of an undesirable parasitic capacitance on the read bit line. The increase of the undesirable parasitic capacitance may delay a period of pulling up the read data to the full logic level at the read bit line. Accordingly, the sense amplifier is slow to output the read data, thereby increasing a data access time of the memory device.
SUMMARY OF THE INVENTION
It is, therefore an object of the present invention to provide an apparatus for sensing a current direction of an input signal and amplifying the sensed input signal to a logic level in use for semiconductor memory devices, in which an erroneous operation can be prevented and a data access time therein can be greatly improved.
It is, therefore, another object of the present invention to provide an apparatus for sensing a current direction of an input signal and amplifying the sensed input signal to a logic level in use for semiconductor memory devices, comprising; a current-direction sensing and amplifying means for a sensing a current direction of the input signal and amplifying the input signal in response to a sensing control signal to output a sensed and amplified signal; and a voltage level shift means for receiving a reference voltage from an external circuit and shifting a voltage level of the sensed and amplified signal to output a level shifted signal.
REFERENCES:
patent: 4140958 (1979-02-01), Groeschel
patent: 4984204 (1991-01-01), Sato et al.
patent: 5706236 (1998-01-01), Yamamoto
patent: 5789948 (1998-08-01), Kim et al.
patent: 5838515 (1998-11-01), Mortazavi et al.
patent: 5844427 (1998-12-01), Theus et al.
patent: 6099032 (1999-12-01), Lin et al.
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Nelms David
Yoka Connie C .
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