Apparatus for saving power consumption in semiconductor memory d

Details Apparatus for saving power consumption in semiconductor memory d Apparatus for saving power consumption in semiconductor memory d

1997-12-30

1999-07-20

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, 36523008, G11C 800

Patent

active

059264357

ABSTRACT:
A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.

REFERENCES:
patent: 4970687 (1990-11-01), Usami et al.
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5379261 (1995-01-01), Jones, Jr.
patent: 5600606 (1997-02-01), Rao
patent: 5701273 (1997-12-01), Choi
patent: 5745429 (1998-04-01), Cowless et al.

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