Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-04-19
2005-04-19
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S005000, C710S007000, C710S020000, C710S021000, C710S036000, C710S040000, C710S053000, C710S056000
Reexamination Certificate
active
06883045
ABSTRACT:
An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.
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U.S. Appl. No. 09/399,281, filed Sep. 17, 1999.
Askar Tahsin
Chambers Eric G.
Curran Stephen J.
Farooq M
Gaffin Jeffrey
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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