Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-05-10
2003-05-06
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S346000
Reexamination Certificate
active
06560304
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to signal transmission and reception, and in particular, to an apparatus that reduces pattern jitter and a method using the same.
2. Background of the Related Art
In general, when a signal is transmitted and received between a transmitting terminal and a receiving terminal in data communications, the signal transmitted from the transmitting terminal is received by the receiving terminal, and then, a timing phase of the received signal must be recovered. Recovering the timing phase implies finding an exact sampling timing from the received signal to regenerate the exact transmitted signal.
For example, in accordance with a nonlinear spectral line timing recovery, which is popularly used in an analog field, a carrier is removed from a received signal (in an analog type), and a tone signal is generated by squaring the received signal with its carrier removed. A timing phase signal of the received signal is generated by filtering the tone signal, and thus, the transmitted signal is regenerated.
For example, in accordance with a discrete-time nonlinear spectral line timing recovery, which is utilized in a digital field, an oversampling is carried out on a received symbol signal. A timing phase signal of the received signal is generated by carrying out a filtering or a digital fourier transform DFT on the oversampled signal, and thus, the transmitted signal is regenerated.
When the timing phase of the received signal is recovered by the above-described methods, even if a channel noise is small, a timing error occurs that makes it difficult to find an exact sampling timing of the received signal. In particular, when the transmitted signal from the transmitting terminal has a pattern of “. . . 1, 1, 1, . . . ” or “. . . −1, −1, −1, . . . ”, even if a nonlinear operation unit for squaring the received signal of the receiving terminal serves to generate a nonlinear signal, a tone signal of the nonlinear signal is small, and thus, noise is inserted into the timing phase signal. The error is called a “pattern jitter” or a “self-noise”.
A related art apparatus for reducing the pattern jitter will now be described.
FIG. 1
is a schematic view of the related art apparatus for reducing the pattern jitter. The apparatus includes an A/D (analog/digital) converter
10
receiving a symbol signal DIN and sampling the N symbol signals with a sampling frequency f. The A/D (analog/digital) converter
10
outputs a received signal D
1
, which is convoluted with a raised cosine wave. A prefilter
12
filters the received signal D
1
and outputs a first filtering signal D
2
. A nonlinear operation unit
14
squares the filtering signal D
2
to output a nonlinear signal D
3
, and a bandpass filter
16
bandpass-filters the nonlinear signal D
3
to output a second filtering signal D
4
. A phase detector
18
detects a phase of the second filtering signal D
4
, and outputs a timing phase signal DOUT.
A method for reducing the pattern jitter using the related art apparatus for reducing the pattern jitter will now be described.
FIG. 2
illustrates a raised cosine wave signal inputted to the prefilter and a quasi locally symmetric wave signal QLS outputted from the prefilter to show a principle for reducing the pattern jitter with the related art apparatus. When the raised cosine wave signal RC is inputted to the prefilter
12
, the signal outputted from the prefilter
12
is the quasi locally symmetric wave signal QLS, which is symmetric to a peak or a zero-crossing of the raised cosine wave signal RC and has many tone signals.
FIGS. 3A
to
3
C respectively illustrate signals inputted to or outputted from the related art apparatus for reducing the pattern jitter. When the symbol signal DIN is a binary type shown in
FIG. 3A
that is oversampled 8 times higher than the rate of the symbol signal and convoluted with the raised cosine wave signal RC by the A/D converter
10
, the received signal D
1
is outputted from the A/D converter
10
as shown in FIG.
3
B. At this time, the symbol signal and the received signal D
1
have pattern jitter because signals that identically have a positive sign and an amplitude value of ‘1’ are repeated for a symbol time 8 to 32 and a symbol time 48 to 80 as shown in FIG.
3
A. Therefore, in accordance with the above-described functions of the prefilter
12
, the nonlinear operation unit
14
receives the first filtering signal D
2
in the quasi locally symmetric wave signal QLS type, which has a property of limiting a band and is locally symmetric to each point indicating integer times of a symbol period as shown in FIG.
3
C. Here, the first filtering signal D
2
has a value of ‘0’ (zero) on the point indicating the integer times (excluding ‘0’ (zero)) of the symbol period. Accordingly, an interference between the symbol signals is removed. However, the interference still remains on the other points.
The nonlinear operation unit
14
outputs the nonlinear signal D
3
only having a positive value by squaring the first filtering signal D
2
. The bandpass filter
16
, which has a center frequency identical to a frequency of the symbol rate, receives the nonlinear signal D
3
and outputs the second filtering signal D
4
in a sinusoidal wave type.
The phase detector
18
, which receives the second filtering signal D
4
, serves to output the timing phase signal to be regarded as an optimal sampling timing of the symbol signal. The optimal sampling timing is a timing corresponding to a peak or a zero-crossing of the second filtering signal D
4
. In accordance with the related art method for recovering the timing phase by utilizing the prefilter, the pattern jitter can be reduced by generating a signal in the quasi locally symmetric wave signal QLS type to provide sampling timing information regardless of a pattern of the symbol signal.
However, the related art apparatus and method have various disadvantages. The prefilter of the related art requires a large amount and complex hardware. That is, the prefilter including M taps needs as many multipliers as the number of the taps (M), M−1 adders and M−1 memory devices, which make the related art system bigger. This disadvantage is especially severe when a very large scale integration VLSI is embodied because the multiplier consumes a large amount of electricity as well as takes a large portion of a chip. In addition, the related art method for recovering the timing phase has another disadvantage in that the number of the operations carried out on the symbol signal increases in proportion to the number of the taps in the prefilter.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an apparatus and method for reducing pattern jitter that substantially obviates one or more disadvantages caused by limitations of the related art.
Another object of the present invention is to provide an apparatus for reducing a pattern jitter of a symbol signal and a method using the same that determines a timing phase of the symbol signal.
Another object of the present invention is to provide an apparatus for reducing a pattern jitter that requires reduced hardware or consumes a less power.
Another object of the present invention is to provide an apparatus and method that can reduce a specific pattern jitter of a symbol signal by using a local symmetry forcing wave generating unit when a timing phase of the symbol signal is recovered.
In order to achieve at least the above-described objects in a whole or in parts, there is provided an apparatus for reducing a pattern jitter according to the present invention that includes a demultiplexer that receives an input including a preamble signal and a data signal from an analog/digital (A/D) converter; a nonlinear operation unit that receives the preamble signal; a locally symmetric wave generating
Hwang In Seok
Lee Yong Hoon
Yoon Young Bin
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Lugo David B.
LandOfFree
Apparatus for reducing pattern jitter by using locally... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for reducing pattern jitter by using locally..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for reducing pattern jitter by using locally... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3006923