Apparatus for reducing leakage in global bit-line architectures

Details Apparatus for reducing leakage in global bit-line architectures Apparatus for reducing leakage in global bit-line architectures

2007-12-05

2009-11-17

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S198000, C365S189050

Reexamination Certificate

active

07619923

ABSTRACT:
A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.

REFERENCES:
patent: 5504709 (1996-04-01), Yabe et al.
patent: 5862074 (1999-01-01), Park

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