Apparatus for reducing electrical shorts from the bit line...

Details Apparatus for reducing electrical shorts from the bit line... Apparatus for reducing electrical shorts from the bit line...

2005-05-17

2005-05-17

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000

Reexamination Certificate

active

06894332

ABSTRACT:
A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

REFERENCES:
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5563089 (1996-10-01), Jost et al.
patent: 5686747 (1997-11-01), Jost et al.
patent: 5763306 (1998-06-01), Tsai
patent: 5821140 (1998-10-01), Jost et al.
patent: 5946568 (1999-08-01), Hsiao et al.
patent: 6124626 (2000-09-01), Sandhu et al.
patent: 6162737 (2000-12-01), Weimer et al.
patent: 6200855 (2001-03-01), Lee
patent: 6243285 (2001-06-01), Kurth et al.
patent: 6274423 (2001-08-01), Prall et al.
patent: 6300667 (2001-10-01), Miyamoto
patent: 6323080 (2001-11-01), Parekh
patent: 6376301 (2002-04-01), Parekh et al.
patent: 6399982 (2002-06-01), Derderian et al.
patent: 6482245 (2002-12-01), Liu et al.
patent: 6524907 (2003-02-01), Parekh et al.

Affiliated with

Also associated with

Rating

Apparatus for reducing electrical shorts from the bit line... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for reducing electrical shorts from the bit line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for reducing electrical shorts from the bit line... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3410840