Apparatus for reducing current consumption in a CMOS inverter ci

Details Apparatus for reducing current consumption in a CMOS inverter ci Apparatus for reducing current consumption in a CMOS inverter ci

1994-09-16

1996-02-13

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326121, H03K 19003

Patent

active

054914299

ABSTRACT:
A method and system for reducing pass-through current. The amount of simultaneous current flow through p-channel and n-channel devices of a CMOS inverter is reduced. This results in an increase in the power efficiency of CMOS oscillators, inverters, gates and other CMOS circuits. Another benefit of this invention is the increase of the output signal magnitude. This increase in the output signal with the lower power consumption yields a significantly higher efficiency of the CMOS circuit such as an oscillator.

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