Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2005-05-03
2005-05-03
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230080
Reexamination Certificate
active
06888762
ABSTRACT:
A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.
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Ma Manny Kin F.
Shirley Brian
Tran M.
TraskBritt PC
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