Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-07-25
2003-09-23
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230080
Reexamination Certificate
active
06625068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated memory circuits and, more specifically, to techniques for limiting bleed current in row-to-column shorts within dynamic random access memory array circuitry.
2. State of the Art
Integrated circuit technology has come a long way, from a few random transistors fabricated on a single die to extremely complex and dense microprocessing units and random access memory devices currently available. Memory circuits, such as dynamic random access memory (DRAM) arrays, have increased in complexity and density over time. With such increased density and complexity, it is very likely that one or more shorts will occur between a word line (generally referred to as a “row” within the array) and a digit line (generally referred to as a “column” within the array).
A row-to-column short typically is a point defect that shorts together a particular row line to a perpendicular digit line. Such a defect generally ruins the integrity of both the row and column. Spare rows and spare columns are created within the DRAM array in combination with address redirection circuitry in order to substitute functional spare rows and columns for those that are shorted—at least to the extent that shorted rows and columns do not exceed the number of spare rows and columns. Even though this on-chip redundancy allows for the repair of a DRAM integrated circuit device, it is important to note that the shorted columns and rows are not disconnected from the array circuitry. The shorted columns and rows are merely no longer addressed by the array's address decode circuitry. Disconnection of the shorted rows and columns from the array circuitry is impractical—if not impossible—with presently available technology due to the small interword line and interdigit line pitch used to fabricate DRAM arrays. Schemes for implementing row and column redundancy in DRAM arrays are well known in the art, and it is not necessary to further detail these structures at this time.
The repair of row to column shorts through redirected addressing does not eliminate the presence of shorts within the array, nor does it eliminate the potential for biased voltage pull down with the attendant problems of excessive standby current, read/write operations resulting in invalid data and possible damage to cell capacitors within the array. For example, one serious problem is that of an increase in the quiescent standby current because of a defect in the circuit. In standby mode, all the row lines are actively held to ground, while the digits are ideally held to an intermediate supply also known as DVC2 (V
cc
/2), in anticipation of a new access. The row-to-column short therefore acts to short DVC2 to ground, giving a much higher standby current than is otherwise necessary or desired.
Since such short defects cannot be eradicated entirely, large DRAM arrays have resorted to the use of “bleeder” circuits, which act to limit the amount of supply current that actively holds a digit line to DVC2. A schematic example of a low-current bleeder device used in the prior art is depicted in drawing
FIGS. 1A and 1B
, where drawing
FIG. 1A
is the schematic electronic diagram while drawing
FIG. 1B
is a schematic typography of a fabricated memory array. Two, or more, NMOS transistors
10
accompany an equilibrating polysilicon gate transistor
12
to provide a bias level to V
CC
volts. Transistors
10
and
12
operate in conjunction with equilibration to ensure that the digit line pair remains at the prescribed voltage for sensing. Patent digit lines D and D* are a complementary pair that is at V
cc
and ground equilibrate to Vcc/2 volts. The bias devices ensure that this occurs and also guarantee that the digit lines remain at Vcc/2, despite leakage paths that would otherwise discharge them. A current limiting device
14
is placed in series between the shared node
16
, which is a polysilicon gate tied to VCC, and DVC2 bias voltage generator bus
18
(also known as Vcc/2). Current limiting device
14
is a long length (long L), low-current bleeder device
14
that limits the amount of supply current by actively holding the digit line to DVC2. For this example, the row line, which is held low in t
RP
for the time necessary to precharge the row because the row is shorted with the column, leaks some current through the transistor
12
when the equilibrate line is held high during t
RP
. Typically, current limiting device
14
limits the current of a row-column short to approximately 10 microamperes (&mgr;A), which is substantially under the standby current specifications.
As DRAM array sizes grow, however, row-to-column shorts become more prevalent. As such, there is a desire to reduce this current even further to yield dice with a substantial number of row/column shorts and to keep the quiescent standby current in a more tightly controlled range. Unfortunately, the dimensions of current limiting device
14
limit the amount of current that can be reduced and the row-to-column shorts cause current limiting device
14
to operate in a high-current mode. Accordingly, what is needed is a memory array current limiting circuit that reduces the amount of current drawn even further without necessarily having to reduce the size of the bleeder transistor.
SUMMARY OF THE INVENTION
According to the present invention, a DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to levels lower than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.
REFERENCES:
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patent: 5552739 (1996-09-01), Keeth et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5732033 (1998-03-01), Mullarkey et al.
patent: 5734617 (1998-03-01), Zheng
patent: 5982688 (1999-11-01), Han
patent: 6078538 (2000-06-01), Ma et al.
patent: 6226221 (2001-05-01), Ma et al.
patent: 6310802 (2001-10-01), Ma et al.
Ma Manny Kin F.
Shirley Brian
Tran M.
TraskBritt
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