Apparatus for receiving data packet eliminating the need of...

Details Apparatus for receiving data packet eliminating the need of... Apparatus for receiving data packet eliminating the need of...

2006-04-04

2006-04-04

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C710S056000, C365S189011, C365S230010

Reexamination Certificate

active

07024498

ABSTRACT:
A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

REFERENCES:
patent: 5594700 (1997-01-01), Ward et al.
patent: 6678861 (2004-01-01), Jones et al.
patent: 2003/0227943 (2003-12-01), Hallman et al.
patent: 2004/0047367 (2004-03-01), Mammen
patent: 211978 (1999-05-01), None
patent: 2000046371 (2000-07-01), None

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