Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Patent
1998-12-07
2000-12-19
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
710 53, G06F 1300
Patent
active
061638528
ABSTRACT:
One embodiment of the present invention provides an apparatus for receiving data from a synchronous random access memory. This apparatus receives a stream of data along with a data clock signal from the synchronous random access memory. This stream of data is alternately clocked into a first memory register and a second memory register using the data clock signal. At the same time, data is alternately clocked from the first memory register into a first system register, and from the second memory register into a second system register using a slower-speed system clock. These data transfers are coordinated by a controller, which ensures that data transfers from the synchronous random access memory into the memory registers do not interfere with data transfers from the memory registers into the system registers. More specifically, the controller ensures that in a first phase the first memory register is loaded from the synchronous random access memory while the data is being transferred from the second memory register into the second system register. In a second phase, the controller ensures that the second memory register is loaded from the synchronous random access memory while the data is being transferred from the first memory register into the first system register. In a variation on this embodiment, the first and second memory registers are composed of a plurality of separately-clocked data words.
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Heckler Thomas M.
Micro)n Technology, Inc.
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