Apparatus for real-time arbitration between masters and...

Details Apparatus for real-time arbitration between masters and... Apparatus for real-time arbitration between masters and...

2011-07-05

2011-07-05

Misiura, Brian T (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S028000, C710S036000, C710S240000, C710S243000

Reexamination Certificate

active

07975086

ABSTRACT:
A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.

REFERENCES:
patent: 6301642 (2001-10-01), Jones et al.
patent: 6859852 (2005-02-01), Jahnke et al.
patent: 7120714 (2006-10-01), O'Connor et al.
Computers Without Clocks—taken from Scientific American—Aug. 2002—11 pages.
Clockless Chips—taken from Technology Review—Oct. 2001—7 pages.

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