Apparatus for read/write-access to registers having register fil

Details Apparatus for read/write-access to registers having register fil Apparatus for read/write-access to registers having register fil

1997-09-12

2000-03-21

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711100, 711154, 711157, G06F 1200

Patent

active

060413875

ABSTRACT:
A data processing unit has a set of data registers and a set of address registers. Each register has a width of n bits. Furthermore, there are provided address load and store buffers associated with the address registers, data load and store buffers associated with the data registers and a bus having a plurality of bus lines being connected to the store buffers. A data memory unit is connected to the bus. The data registers are arranged in such a way that at least n data registers are connected in parallel to respective bus lines, n being greater than 1, and the address registers are arranged in such a way, that at least m address registers are coupled in parallel to respective bus lines, m being greater than 1. Thus, at least four registers can be accessed in parallel.

REFERENCES:
patent: 4313162 (1982-01-01), Baun et al.
patent: 5649229 (1997-07-01), Matsuzaki et al.

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