Apparatus for random parity check and correction with BCH code

Details Apparatus for random parity check and correction with BCH code Apparatus for random parity check and correction with BCH code

2011-08-23

2011-08-23

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S786000

Reexamination Certificate

active

08006171

ABSTRACT:
An apparatus for random parity check and correction with BCH code is provided, including a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, a channel, a BCH parity check code decoder, and a static random access memory (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

REFERENCES:
patent: 7831895 (2010-11-01), Lin
patent: 2007/0253496 (2007-11-01), Giannakis et al.
patent: 2008/0028274 (2008-01-01), Lin
patent: 2008/0126908 (2008-05-01), Lin
patent: 1226758 (2005-01-01), None

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