Apparatus for providing additional latency for synchronously acc

Details Apparatus for providing additional latency for synchronously acc Apparatus for providing additional latency for synchronously acc

1998-11-25

2000-02-29

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518912, 365194, 365239, G11C 800

Patent

active

060317876

ABSTRACT:
One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and the output register. In this embodiment, the memory system further includes a clock signal coupled to the clocked interface of the memory. The clock signal feeds through a delay element into a clock input of the output register. This causes the output register to receive a delayed clock signal, thereby providing more than one clock cycle of time for data to be read from the memory and latched in the output register. In another embodiment, the present invention provides an input register, for inputting data during write operations. This input register similarly receives a delayed clock signal, which functions as an advanced clock signal from the preceding clock cycle to provide more than one clock cycle of latency for write accesses to memory.

REFERENCES:
patent: 5224072 (1993-06-01), Matsubara
patent: 5440515 (1995-08-01), Chang et al.
patent: 5530670 (1996-06-01), Matsumoto
patent: 5701436 (1997-12-01), Nagashima et al.
patent: 5767715 (1998-06-01), Marquis et al.

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