Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-10-13
2003-03-11
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S167000, C711S005000
Reexamination Certificate
active
06532523
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer memory and more particularly to an apparatus for processing memory access requests involving multiple banks of SDRAM memory.
2. The Background Art
Modern electronic systems utilizing Synchronous Dynamic Random Access Memory (SDRAM) for temporary data storage often employ one or more memory devices. Typical memory arrays are thought of as being rectangular, with a given memory cell in an array being accessed when the proper row and column lines are asserted.
In order for a device to access memory, the device typically provides required information to a memory manager, and the memory manager then interacts with the memory device to perform the required operation. The memory manager is responsible for determining which memory component to interact with for the desired operation, and then performing the operation in the correct manner. Thus, the device requesting the operation typically does not know the physical characteristics of the memory, whether other devices have initiated other memory operations, etc. However, the throughput devices requiring memory operations are greatly affected by the throughput of those memory operations.
Typical memory devices are organized in banks of memory cells. It is normal for data pertaining to a given device to span more than one bank. Further, devices commonly access data without regard to the bank in which that data is stored. Therefore, a device may first access data stored in one bank and then access data in a second bank in the following operation.
Prior art memory managers operate on each bank of memory in serial fashion. Using a prior art apparatus, a read or write operation involving one bank of memory must be fully completed prior to a succeeding operation on a different bank being initiated. As those of ordinary skill in the art are readily aware, a typical write operation involves a row command, a column command, and a precharge command. Correspondingly, a read operation typically involves a row command, a column command, two wait cycles while data is retrieved from memory, and a precharge command.
Although performing memory operations in serial fashion is useful for its intended purpose, prior art memory operations are not performed at the highest possible throughput. Therefore, the devices requiring these operations do not operate at their peak efficiency, due to the less than optimal efficiency of the memory operations.
It would therefore be beneficial to provide an apparatus and method for performing memory operations at a higher throughput than the prior art.
SUMMARY OF THE INVENTION
The present invention provides an improved apparatus for processing memory access requests, the apparatus comprising a first state machine for controlling access to a first memory bank, a second state machine for controlling access to a second memory bank, and an arbiter. According to the invention, while the first state machine is processing a current memory access request to access the first memory bank, the arbiter receives a next memory access request. In response, the arbiter determines whether the next memory access request will interfere with the processing of the current memory access request. If the next memory access request will not interfere with the processing of the current memory access request, and if the next request is directed to the second memory bank, then the second state machine is allowed to begin processing of the next memory access request prior to the completion of the processing of the current memory access request by the first state machine. In one embodiment, the second state machine begins processing of the next memory access request during one or more of the mandatory wait periods implemented by the first state machine. Thus, the first and second state machines are allowed to process the current and next memory access requests concurrently. By taking advantage of the wait periods of one state machine to get an early start for another state machine, the present invention significantly reduces the amount of wait time required in processing memory access requests. This in turn significantly improves the throughput and the overall efficiency of the memory system.
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Encarnación Yamir
Oak Technology, Inc.
Schipper John F.
Truong Bobby K.
Yoo Do Hyun
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